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A variety of CMOS gates

In Electronic Infomation Category: A | on February 09,2012

A. The principle and 2SK2134 datasheet and structure
, MOS transistor in a CMOS integrated circuit N-channel enhancement type MOS transistor and 2SK2134 price and the P-channel enhancement MOS transistor. N-channel enhancement type MOS transistor structure shown in Figure 2.13. A low impurity concentration P-type silicon substrate (B), in which the diffusion of two N + regions as electrodes, which are called source (S) and 2SK2134 suppliers and drain (D). Semiconductor surface covered with a Si02 insulating layer on the insulating layer between the drain-source and then sputtering a layer of metallic aluminum, known as the gate (G).

G and S-voltage drain-source pole between the two back of the PN junction, so there will not be a drain current after the voltage is between the D, S. Assume that D, S between the short-circuit, G, S-plus positive voltage, as shown in Figure 14 (a). Plus the forward voltage between the gate, the substrate, the metal gate charge and gather positive charge in the P-type semiconductor electronic empty six positive charge exclusion, left on the surface of negatively charged ions, the formation of the depletion layer. With the G and S a positive voltage increase, the depletion layer widening. When the Ucs increased to a certain value, the substrate in the electronic gate in the positive charge to attract to the surface to form an N-type thin layer between the depletion layer, called the inversion layer, as shown in Figure 2.14 ( b) below. The inversion layer form a conductive channel between drain-source. Voltage between D, S, similar to the above situation will not repeat them.

P channel enhancement MOS transistor is an N-channel enhancement type MOS transistor of dual analysis to analyze the N-channel enhancement mode MOS tube.

2. CMOS NAND gate
2.15 as shown in the CMOS NAND gate, TN dike N-channel enhancement type MOS transistor TP is a P-channel enhancement type MOS transistor, connected into the two complementary symmetry of the structure. Their gate connected as a signal input terminal, and drain connected together as a signal output, TN source grounded, the TP of the source power supply VDD.

(1) when the input A low O, TN deadline, TP conduction, the output y for the high l;
(2) when the input A is high 1 TP cut-off of TN conduction, the output y is low 0. The foreseeable circuit

non-logical functions.

3. CMOS NAND gate
Figure 2.16 shown in the CMOS NAND gate circuit. Two P-channel enhancement mode MOS transistor TP1 and TP2 in parallel, in series, the two N-channel enhancement type MOS transistor TN1 and TN2. TP1 and TN1 gate connected as an input A, TP2 and TN. Gate connected as an input B.

(1) A and B, in one or all low O of TN1, TN2 one or all of the cut-off, TP1, TP2 one or all of the conduction, the output y is Level 1.

(2) when A and B for high 1 of TN1 and TN2 only conduction TP1 and TPZ will close the output y will be low. The foreseeable circuit

and non-logic functions. . CMOS NOR gate,


2.17 as shown in the CMOS NOR gate circuit. TN. N-channel enhancement type MOS transistor TN2 is, both in parallel; TP1 and TP2 enhanced P-channel MOS transistor, the two series. TP1 and TN1 gate connected together as the input A, TP2 and TN2 gate connected together as the input B

(1) A, B, in one or all high, TP1, TPZ in one or all of the cut-off, of TN1 of TNZ in one or all of the conduction, the output y for low level O.

(2) when A and B for low O, TP1 and TPZ will have conduction of TN1 and TN2 will close output y will be high one.

visible circuit or non-logical functions.

5. CMOS tri-state the door
Figure 2.18 shown in the CMOS tri-state gate. TNI and TN2 is N-channel enhancement type MOS transistor, the two series; TP1 and TP2 are the P-channel enhancement type MOS transistor, both also in series. TPI and the TN1 gate connected together as the input A, TP2 and TN2 gate connected together as control side.

(1) E 1, TP:, TN2 are cut-off, y-, and ground and power supply disconnected output presents a high impedance state.
(2) E-O, TP2, TN2 conduction, TP1, of TN1 constitute the inverter. The foreseeable circuit output

high impedance state, three kinds of high and low state, a tri-state gate.

6. CMOS transmission the door
Figure 2.19 shown in the CMOS transmission gate. TN is the N-channel enhancement type MOS transistor, the TP is a P-channel enhancement type MOS transistor. Gate G, two of TP and TN respectively, then complementary control signals C and C, T, and Tr the two source and drain, respectively, together as the input side and output side of the transmission gate.

(1) C 0, C = l, the C-terminal low (OV), C-side is high (+ VDD), TN and TP do not have to open conditions while the cut-off between input and output is equivalent to switch off the same.

(2) C 1, CO,, C-terminal is high (+ VDD), C-side is low (OV), TN and TP with the conduction conditions, input and equivalent to switching between the output connected to the same ".

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