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How in the DS26303 LIU enable ITU-T G.703 2048kHz Synchronization Interface (T12)

In Electronic Infomation Category: H | on May 07,2011

Abstract: maintaining multiple clock synchronization between the telecommunications equipment is the basic function of any large facility. ITU-T G.703 2048kHz Synchronization Interface (T12) specification provides a common clock distribution method. Although the DS26303 E1/T1/J1 eight-channel line interface unit (LIU) fully support the specification, but it needs some additional configuration to ensure proper operation. This application note describes how to enable 2048kHz synchronization interface mode, and LTC3411EMS datasheet and how to configure the DS26303, to support the clock distribution applications.

Introduction

DS26303 E1/T1/J1 eight-channel line interface unit (LIU) is a little-known features: the ability to launch, receive meet the International Telecommunication Union ITU-T recommendation G.703 (2001 Nian 11 months) the provisions of Article 13 The 2048kHz Synchronization Interface (T12) signal. This application note describes how to program correctly DS26303, 2048kHz synchronization interface mode is enabled to support the Integrated Timing Supply System (BITS) or the regular supply unit (SSU) and LTC3411EMS price and other clock distribution applications. It should be noted, there are currently two products available DS26303: DS26303-120 and LTC3411EMS suppliers and DS26303-75. The only difference between the E1 line impedance is the default setting. Must pay attention to this feature, ensure that the design phase and production phase of the same type of device.

DS26303 set the work in the 2048kHz synchronization interface mode

On the DS26303 programmed to support the 2048kHz synchronization interface, the process requires multiple steps, use the data that are not listed in the table in the DS26303 register. This "Appendix" shows all the registers not listed in the instructions.

2048kHz synchronization interface mode is enabled, it is necessary to perform some configuration operations to ensure DS26303 work according to the required process.

First step, change the internal clock, using the corresponding channel send LIU clock (usually TCLK input) to replace the master clock (MCLK input). By default, enable 2048kHz synchronization interface mode, DS26303 MCLK input will be used as a general-purpose clock source. This will TTIP / TRING pins MCLK output signal locked to the input, rather than the TCLK input. Can use the following software configuration on the DS26303 programming, using as the TCLK input clock source.

Will address the ADDP register is set to 0x1F 0x03, select the global test registers.

The TXDIG the address register is set to 0x07 0x10. 4 to register the location TXDIG 1,2048 kHz synchronous interface mode will use the TCLK input, rather than the MCLK input. Note that, change the first four TXDIG register will affect the MCLK input as the clock source of the other two functions, namely: launch full-1 (TAOE) and automatically launch all 1 (ATAOS) function. Therefore, disabling 2048kHz synchronization interface mode, you need the position 0. However, if you enable TAOE or ATAOS, designers want to TCLK input as a clock source, you can register to TXDIG 4 position 1.

Second step, change the short-circuit detection circuit (SCDC) of the current threshold, to prevent the closure TTIP / TRING transmitter output. By default, enable 2048kHz synchronization interface mode, DS26303 current threshold is not correct. To take advantage of the right to set short-circuit current DS26303, to carry out the following software configuration.

Will address the ADDP register is set to 0x1F 0x04 to 0x0B, will choose to LIU8 LIU1 test test registers.

The address register is set to 0x05s TXCMDA one of the following values ??(Table 1), these values ??should be the template selection (TS) register values ??simultaneously. For example, if the TS mode register is configured as E1 75, then TXCMDA register is set to 0x33. In addition, enable G.703 2048kHz Synchronization Interface mode, the launch should not close the TS register impedance termination. Note, TXCMDA register bits 7:6 should always remain 0; the first five control SCDC control enabled; No. 4:0 bit includes a new short-circuit current threshold, although the limit can be adjusted door, but not recommended, because choose these values ??to prevent device damage.

Table 1. TXCMDA register settings

TS Mode Setting

TXCMDA Value

E1 75

0x33 < / SPAN>

E1 120

0x2F < / SPAN>

The completion of these two configuration steps, DS26303 is correctly configured to support 2048kHz Synchronization Interface mode. DS26303

set of one or more channels, to support the 2048kHz synchronization interface mode, in accordance with the following software configuration.

The address register is set to 0x1F of ADDP 0x01, select independent LIU register.

Will address the G703EN register 0x08 is set to the required value, the LIU for the appropriate channel to enable the 2048kHz synchronization interface mode.

Assume that the proposal has been disabled in accordance with the above TTIP / TRING emission output, the following software configuration is enabled through the transmitter output.

The address register is set to 0x1F of ADDP 0x00, select the main register.

Register the address 0x12 of the OEB is set to the required value, in order to register for the opening of the same G703EN LIU channel enable TTIP / TRING transmitter output.

Conclusion

Of DS26303 change the default values, the device can fully support the ITU-T G.703 2048kHz Synchronization Interface (T12) specification. This application note describes the necessary changes, as well as relevant background information and describes in detail the configuration process. With this information, and DS26303 data, designers can 2048kHz synchronization interface features into the design of BITS or SSU.

Appendix: DS26303 register information

DS26303 register address space 0x00 to 0x1F, using memory mode, LIU channel contains all the configuration and status information. The ADDP register address 0x1F as a special register, store a pointer to access the different registers. For each specified register, the register functions and values ??remain unchanged. However, the changes of ADDP register will change the current register in order to change address 0x1E 0x00 to the register function and value.

The following elements to enable ITU-T G.703 2048kHz Synchronization Interface (T12) detailed information needed to register, as well as every description.

Register Name: ADDP

Register: present in all registers

Register Description: The address pointer

Register address: 1Fh

Bit #

7

6

5

4

3

2

1

0

Name

ADDP7 < / SPAN>

ADDP6 < / SPAN>

ADDP5 < / SPAN>

ADDP4 < / SPAN>

ADDP3 < / SPAN>

ADDP2 < / SPAN>

ADDP1 < / SPAN>

ADDP0 < / SPAN>

Default

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

No. 7-0: address pointer (ADDP). Used to select, switch the main register, Vice register independent registers LIU, BERT registers and a pointer to any test register. For example, the software must be set ADDP register 0x00, to access the main register; set to 0xAA, deputy register to access; set to 0x01, LIU register to access independent group; or set to 0x02, to access BERT registers. Please refer to Table 2, learn how to select the appropriate register.

Table 2. Address pointer register selection

ADDP RegiSTer Value

Register Bank NAME

0x00 < / SPAN>

Primary < / SPAN>

0xAA < / SPAN>

SecONdary < / SPAN>

0x01 < / SPAN>

Individual LIU

0x02 < / SPAN>

BERT < / SPAN>

0x03 < / SPAN>

Global Test

0x04 < / SPAN>

LIU1 Test

0x05 < / SPAN>

LIU2 Test

0x06 < / SPAN>

LIU3 Test

0x07 < / SPAN>

LIU4 Test

0x08 < / SPAN>

LIU5 Test

0x09 < / SPAN>

LIU6 Test

0x0A < / SPAN>

LIU7 Test

0x0B < / SPAN>

LIU8 Test

Register Name: G703EN

Register: Independent LIU register

Register Description: ITU-T G.703 2048kHz Synchronization Interface is enabled

Register Address: 08h

Bit #

7

6

5

4

3

2

1

0

Name

G703EN7 < / SPAN>

G703EN6 < / SPAN>

G703EN5 < / SPAN>

G703EN4 < / SPAN>

G703EN3 < / SPAN>

G703EN2 < / SPAN>

G703EN1 < / SPAN>

G703EN0 < / SPAN>

Default

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

0 < / SPAN>

No. 7-0: G703 Enable (G703EN). When this bit to 0, the associated LIU channel transmitter and receiver in a normal T1/E1/J1 mode. The position 1, the associated LIU channel transmitter and receiver in the ITU-T G.703 2048kHz Synchronization Interface (T12) model.

Note: This feature is only available in A2 and later devices.

Register Name: TXCMDA

Register: LIU Test Register Group 1 Zhi 8

Register Description: Launch a custom mode line driver A

Register Address: 05h

Bit #

7

6

5

4

3

2

1

0

Name

Reserved < / SPAN>

Reserved < / SPAN>

SCDCOR < / SPAN>

SCC4 < / SPAN>

SCC3 < / SPAN>

SCC2 < / SPAN>

SCC1 < / SPAN>

7

6

5

4

3

2

1

0

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