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H.264 video decoding chip, memory associated with the design of filter

In Electronic Infomation Category: H | on May 04,2011

Abstract: The H.264 decoder chip in the filter part of the required data, data access and AD581SH/883B datasheet and memory chips are used in-depth analysis done, but involves the design of DRAM and AD581SH/883B price and SRAM, and AD581SH/883B suppliers and to support macro block-level adaptive frame field. H.264 decoder chip in order to achieve fast data access, this paper presents an optimization of the data storage method, this method can be fully achieved through the filtering process in the handling of large amounts of data. Results show that this method can save memory resources and meet the H.264 filter in the large amount of data processing requirements.

H.264 video coding standard as a new generation has a superior performance, are widely used in video conferencing, video on demand, digital television broadcasting, digital video storage and consumer electronics and other fields. With H.263 or MPEG-4 compared to the same image quality, the bit rate can be reduced about half, but the algorithm complexity is high.

H.264 standard in the case of low bit rate can produce high quality images, mainly using the adaptive loop filter. H.264 uses tree-based motion compensation block, block-based motion compensation can well reduce the rate, but also caused a block effect. H.264 uses a

this adaptive filtering algorithm, can well reduce the block effect, but also brought a great deal of computational complexity. In H.264, the filtered data will serve as the next frame of the reference frame, it is also known as the loop filter. The results show that: in the H.264 decoding process in which motion compensation (MC) about 30%, loop filter (DF) accounts for about 20% of the decoding time, so well designed, MC, DF performance of the decoder to the relevant important.

1 used data filtering process

H.264, in the case of decoding MBAFF macro block is macro block to the form. Therefore, data storage is also considered a macro block data is stored as a unit. In a macro block, the filter need to manipulate the whole process when the data shown in Figure 1. In which each small box represents a 4 4 pixel block, the macro block in the filter mb_up need to use up within the meaning of data, this design supports MBAFF, in the filtering process requires the conversion of the frame and field, and therefore used in the above two lines of the block. The left-most block in the filter when the need to use the figure indicated by a left data.

filter the data in Figure 1

2 DRAM in the planning and design

DRAM is a low cost, large capacity storage media widely used for the operation of large-scale data very quickly. However, as there is a DRAM Row concept. Row in the case of operating under a different first close the current DRAM Row, while the required reactivation Row, thus causing a lot of overhead. Just read the same data Row 10 Row 10, respectively, in the 10 data, which will be time consuming 5 to 6 times the former. Therefore, DRAM is not suitable for the dispersion of random data access.

The existence of the Row, on the DRAM in the design of data structures is particularly important. To minimize the difference between Row visit, so as to improve data access efficiency. The design uses 64-bit bit wide DRAM, you can store just 8 points in pixels. Image luminance Y, chrominance UV were stored in a continuous space.

H.264 decoded in the last image stored in DRAM, display module constantly get the data from the DRAM to the display, motion compensation unit should also remove the reference frame from the DRAM data. Therefore, the bandwidth of DRAM is particularly tense. Reasonable distribution of the design of DRAM bandwidth is an important aspect to consider. Since many of the DRAM modules are required to operate, in order to effectively manage the DRAM, set the DRAMCONtrol on the DRAM modules to control.

3 DRAMControl Module

DRAMControl DRAM module controls the interaction with the outside of other modules, is the other modules and external DRAM interface. The main features include auto-refresh DRAM, DRAM production orders and so on. Because the state of DRAM work more, this design approach used to achieve the state machine. One state diagram shown in Figure 2.

Figure 2 DRAMControl the state transition diagram

Design refresh by way of uniform, every certain period of time, after the "IDLE PRECHALL AUTORF IDLE" process to complete a refresh. State transition process of the subject is read and write operations, the verdict states (Decision) takes one clock cycle to determine the current operation is to be executed Row is active, if not the first close the current activated in the active state of Row, and then activate the necessary Row (completed by PRECH and ACT state); If you have activated, directly read and write operations. For a write operation, after filtering for H.264, the macroblock to update the top left macroblock macroblock and its own data to design a WRITEUP or WRITELEFT and WRITE to write the three states DRAM, but also achieved between these states seamless connection time, constitute a complete write coherent BurST; if the upper left of the macro block of data or data blocks in the macroblock and the macroblock to be filtered data blocks of different Row in the state in WRITEUP or WRITELEF Tile is not the realization of the data block write operation, the efficiency of this situation is clearly written in the same Row over time in the fall, but this is inevitable, when the macro block is in the far left or the Row when the top , the top left of the macroblock or macroblock data block must be belong to other Rows. This design, DRAM memory an address block and the next block of the same line, so that to avoid the largest cross-Row operation. Write for other cases, the use of WRITE state of completion.

4 SRAM planning and design

In the H.264 decoding process, the data after motion compensation by entropy decoding and then finally sent to the memory through the loop filter, the decoder chip is displayed after the extraction from the memory data to continuously monitor the eventual data decoding, shown in Figure 3. In the filtering process, the macro block data frequently is called. The SRAM features a fast read and write well to apply this requirement. Because H.264 is the smallest unit of block, motion vector, etc. are to be passed as a unit block. Therefore the block as a unit for data access will bring great convenience. The design of each address of each SRAM cell storing a data block (16 pixels), which uses 128bit of SRAM.

Figure 3 DRAM modules and other data exchange between the

Motion compensation in H.264, the data after the loop filter algorithms to be written by the DRAM, we write this process is known as Store DRAM process, the Store module is responsible. MC can be seen from Figure 3, and Deblock is a series of relationships. To improve the decoding speed, motion compensation will be executed in parallel with the loop filter that is not the end of the current decoding end of the loop filter as a symbol, and the current macro block motion compensation is over we can start the next macroblock decoding. After a number of experiments found: MC of the time much larger than the block of time, when a module to the filter after the filter module when already ready. Finally, we have the same memory modules used in parallel to accelerate the decoding speed of thought. The MC results as MBx when doing MB (x-1) of the filter, while MB (x-2) storage. At this point to note MB (x-1) of the filtering and MB (x-2) storage is not the same start. As do MB (x-1) will also affect the filter when MB (x-2) in the data.

So we have to wait MB (x-1) of the first start after the end of the vertical edge filtering MB (x-2) storage. Specific time shown in Figure 4.

Figure 4, the timing relationship between each module diagram

(1) filter and the filter before the data is stored after the data storage

Such as used in the design process, we need three SRAM to store the results of MCs operations. This three SRAM alternately carried MC, Deblock and Store. We call these three SRAM-SRAM_MB, after filtering data also stored in this SRAM, in this data is stored by the Store to the DRAM modules to go. Because the filter end, just the data in the original SRAM_MB has become invalid data. It should be noted, due to existence of the circumstances adaptive frame field, filter the data after the end of the frame field if the situation is different, we need the data to different circumstances into proper frame field, then after the data stored in DRAM.

(2) vertical filtered data storage

We all know is a filtering process after the first vertical level of the process, so we need to have a level of SRAM to store the filtered results. This SRAM is called SRAM_BUFFER. Because the level of the filtering of data is read from the SRAM_MB the same time can not be read to the SRAM, write the data. So we SRAM_BUFFER to temporary data after the end of the vertical filtering. When the level of filtering in from the SRAM_BUFFER read data stored in the SRAM_MB in filtering.

5 Summary

H.264 decoder chip in this paper, filtering, storage modules in depth analysis. Time data based on the characteristics of each corresponding memory design, this design method can well handle a proven H.264 filter and stored in the data scheduling. About the filtering process can be completed in 52 cycles. In the case of a variety of data MBAFF clock cycle control in the conversion of 70 or less. This design meets the requirements, and verify the FPGA to normal after the operation, run the clock to 60MHz, can be completed in real-time decoding of high definition images.

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