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Position:IcFull.com » IC Electronic information » Category: W

IC Electronic information

Wishbone bus on UART IP Core Design

In Electronic Infomation Category: W | on April 18,2011

With the development of integrated circuits and MOCD223 datasheet and embedded technology with broad applications, many embedded systems require serial communication, so the chip-chip integration of embedded systems uART (universal asynchronous sending and MOCD223 price and receiving device) IP core has become a trend.

IP core reuse-based integrated circuit design, selection of on-chip bus is the most critical issue. Currently, many vendors have developed for each chip bus standard UART IP core, such as AMBA Bus UART IP-based core, based on CoreCONnect bus UART IP core and MOCD223 suppliers and so on. If you want to use these commercial UART core, you need to get authorization. Therefore, from the cost, performance, open the perspective, the use of open source, easy to implement the Wishbone bus standard design of the UART IP core will have broad market.

1 UART IP core design principles

1.1 UART works

Universal asynchronous receiver device (UART) serial communications is an important computer component. It will house computer system to send over the parallel data into serial output data stream is transmitted to level out; will send to the external computer system is converted to byte serial data for internal use parallel data computer system devices use; in the output serial data stream by adding parity bits, and data received from the external flow parity; in the output data stream by adding start and stop tags, and remove from the received data stream status flags.

For the UART, the bus all the signals are essential. These signals include the necessary control information and data. Therefore, the design of the bus determines the UART interface, the design details. This design uses a UART core Wishbone bus to communicate with the host computer system interface. UART core of the interface signals shown in Figure 1.


Figure 1 UART core interface signals

1.2 Wishbone bus interface

In IC design, Wishbone bus architecture is a flexible, open source design. Its purpose is to promote design reuse, simplify SoC integration issues. Created between the IP core through a bus interface, which will all be easily connected IP of nuclear energy. This design improves the reusability and reliability of the system to speed up the speed to market. Prior to this, IP core is used between the non-standard specifications for connecting the bus, which is difficult to achieve reuse. Therefore, the E-bus structure using a standardized IP core design, IC design industry has become mainstream.

In the design, Wishbone bus and UART controller for the computer system provides the operator interface. Wishbone bus interface, the main function is to coordinate between the processor and the UART core signal to the processor core to proper use UART for data communication.

2 UART IP core design and implementation

UART IP core development is in accordance with Wishbone bus RS232 protocols and standards, and integrates the basic functions of UART.

UART IP core of the main technical features include:

(1) supports the standard RSR232 Wishbone bus interface standard and specification.

(2) full-duplex transmit and receive independently.

(3) receiving channel parity, overflow, resulting in an optional interrupt.

(4) built-in support to receive and send 16 Byte FIFO.

(5) send "empty" optional interrupt generation, receive "full" optional interrupt generation.

UART IP core architecture, shown in Figure 2.


Figure 2 UART IP core architecture

UART IP core includes an internal data transmission module, the data receiving module and Wishbone bus interface module. The design of each module are as follows.

2.1 Wishbone bus interface module design

Wishbone bus interface module UART IP core is connected with the computer system. The module provides Wishbone MaSTer and Wishbone Slave interface.

Wishbone bus interface modules main function is as follows:

(1) provides UART IP core interfaces with other devices, such as memory or the host interface.

(2) contains the buffer descriptor (stored in internal RAM).

(3) contains the master clock signal, sending and receiving clock synchronization between the clock logic.

(4) sending. Send buffer descriptor read, read data to the transmit FIFO and start sending, then write transmit buffer will be sent the state descriptor.

(5) reception. Read receive buffer descriptor byte will be written into the receive FIFO, followed by Wishbone Muter interfaces to communicate with the computer system. Finally, the receiving state written to receive buffer descriptor.

When the processor needs to send serial data, the first data packet is stored in main memory, and then all the packages stored in the starting address, destination address, length, and send control information is written to send descriptor in.

Wishbone interface module to read to a non-empty after sending descriptor to send data, send the data to be located by Wishbone bus interface logic to access the main memory, read the data into the transmit FIFO first, its and then by sending control and synchronization logic and data transmission module handshake, the data sent from the TX_O serial port.

When data is received, the data from the serial port to RX_I into receiving FIFO, each received at least 8-bit data to maintain a register into reception and parallel transmission through the Wishbone bus to the processor core.

2.2 data receiver module design

The external signal is transmitted through the asynchronous serial form, so when the receiver detects a high to low port the data to be regarded as a frame start bit. Received signal in order to avoid the noise generated incorrect data, the clock start bit is detected at least 50% lower than the baud rate clock. Once the receiver module receives a valid start bit, it will be through the standard RS232 baud rate of data bits and the parity bit is sampled.

Designed using state machine control receiver module receiving the whole process. Receive state machine can be divided into five states, namely IDLE, RX_START, RX_DATA, CHECK, RX_STOP, state transfer between them, shown in Figure 3.


Figure 3 data receiver module FSM diagram

IDLE state: When the reset signal or running to a stop state, the receiving state machine will be reset to this state. In the IDLE state, it waits for an external signal coming shift from high to low, this time as have a valid start bit. Once a valid start bit is detected, the finite state machine will switch to the next state.

RX_DATA state: When the state machine to jump to this state, have one bit of data for each sample, put the received data into ready to receive shift register. In the design requires a reception counter for counting. When prompted to data reception counter has been completed, the state of opportunity into the next state.

CHECK state: When in the CHECK state, actually received by the data to determine the parity of the actual data obtained, and then sent over the data and parity bits parity.

If so, then the effective receive data that can be passed in the processor; such discrepancies, no transfer, directly discarded data.

RX_STOP status: Regardless of the length of stop bit set to 1 or 2, finite state machine is always waiting for a sample of the sampling time, and then sampling the stop bit. Sampling as long as a logical stop bit is detected, the data receiving module will not check the configuration of the stop bit error. At this time, finite state machine will return to IDLE state.

2.3 data transmission module design

Transmit module receives data from the processor, together with the start bit, parity bit and stop bit serial output after the prescribed format. First, the use of FIFO buffers need to send the data stored, so that one processor can write more bytes to the FIFO data. In order to send data out from FIFO 1Byte each time serial output.

Design uses a state machine to control the sending module to send the entire process. Send state machine composed of the following five states: IDLE, TX_START, TX_DATA, CHECK, TX_STOP, the transfer between them as shown in Figure 4.


Figure 4 data transmit module FSM diagram

IDLE State: In the absence of received data to be sent, the sending module has been in the state, now has to send the module to maintain data bit is high, when the work of the signal sent by the host occurs when the state transition into the next states.

TX_START Status: Send module will first send a data "0", as the start bit. After sending the start bit, into the next state.

TX_DATA Status: After sending the start bit, and then send the valid data coming from the host. First of all the data into the shift register module, the use of parallel input to shift register serial output of the conversion. Counter starts counting at the same time, 8 bits in the transmitted data, the counter is cleared, FSM then jumped into the next state.

CHECK state: When the state machine is in this state, the last one still in the transmission of data. Transfer is complete, the state machine will determine the parity bit. If the parity bit is correct, then into the next state.

TX_STOP state: In this state, according to the sampling results sent the module will set the relevant interrupt and status bits. After transmission, the state machine returns IDLE state.

3 UART IP core of the authentication method

Validation of the UART IP core is mainly in the Modelsim software, a virtual platform for building, through the preparation of Testbench (test code) as the excitation signal, the value will be compared with the expected value to determine the function correctly. Verification system block diagram shown in Figure 5.


verification system block diagram of Figure 5

Imposed by this validation test stimuli consists of two parts, the process of sending data is analog, such as the bus for the internal register read signal module, UART serial output signals and equipment hardware interface signals to verify the normal function of the module is realized; another part of the process of receiving data is analog, such as an external device to send data to the UART receiving process, and the UART to convert the data sent to the computer system. Simulation waveform diagram shown in Figure 6.


Figure 6 Simulation waveforms

Simulation waveform is simulated in full duplex mode, the UART receives a complete data at the same time (51,16 decimal), and send a complete data (11,16 decimal) process. To receive process, for example: UART interrupt signal UART_INT first output is sent to inform the processor ready to receive data, processor interrupt. UART through the sampling pulse (Baud) write RX_UDR receiving the signal register and the receiver counter, counting to 8 is automatically cleared, the interrupt signal automatically cleared, and then will receive the 8-bit data passed through the processor bus module . Send the process to receive the reverse process.

4 Conclusion

IP core reuse technology and IC design interface standardization problem is the research focus areas, and its applications are expanding. This article describes the Wishbone bus-based design method UART IP core, by verifying that the various functions to achieve the desired requirements for the design of IP core interface provides the basis for standardization. In addition, the IP core code used in all modular Verilog-HDL language, to facilitate continuous improvement since, with a strong practical benefits.

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