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Width of the frequency synthesizer used in frequency than the design of CMOS programmable divider

In Electronic Infomation Category: W | on April 28,2011

High-speed, wide frequency range of programmable frequency divider design is the RF frequency synthesizer design difficulties, it is the work of the speed limit of the frequency synthesizer output signal of the highest frequency, its phase noise frequency synthesizer band phase noise device. In this paper, the design of programmable divider tuner for mobile digital TV receiver chip that is compatible with the DVB-H, DAB standard, the receiving band covers 460 ~ 900 MHz, 1 400 ~ 1 500 MHz these two bands. According to the chip system design, the operating frequency is programmable divider 2.4 ~ 4.0 GHz, the divide ratio to achieve the range of 240 to 400, and AD9226AST datasheet and is continuous. Including the current high-speed programmable divider prescaler based on dual-mode pulse swallow frequency divider, and AD9226AST price and based on the basic unit of multi-mode divider two structures, the former because of high speed, simple structure and AD9226AST suppliers and other characteristics, are widely used in RF frequency synthesizer which, at the same time, the programmable divider unit module are coupled based on source (SCL) structure of the analog circuit, as opposed to the low frequency part of the digital standard cells with low noise and small layout area advantages. The number of logical sequence detection and set design is the focus of the design programmable divider, which directly affects the crossover frequency. This paper presents a new detection and set the number of logic and circuit implementation, making the work of the programmable frequency divider 1-fold increase. This paper gives the design of programmable divider r the overall structure and highlight a number of programmable divider logic circuit testing and home improvement programs; Finally, after the layout design and circuit simulation results.

1 programmable divider structure

1.1 overall structural design

Based on a programmable dual-modulus prescaler divider structure shown in Figure 1, which consists of three parts: N / N +1 dual front prescaler, programmable counter, pulse counter swallow .

Figure 1 is based on a programmable dual-modulus prescaler divider structure

Input frequency were first divided by the prescaler, frequency division ratio of the pulse swallow counter gives a signal S Mode control. Swallow programmable counter P and S pulse counter and started counting down, counting down the counter when the S was reduced to 0, Prescaler divide ratio by the N +1 into N, S counter stops counting, P counters continued to cut count; when P counter counts down to 0, through the feedback loop so that P, S re-set the counter number, start a new round of counting. Therefore, each count carried out during the first frequency S N +1 times, and then were divided PS plays N, so the output signal is:

Divide ratio M = PN + S.

Tuner chip system according to the required range and precision frequency synthesis and the use of TSMC 0.13/m process, the design of the dual-modulus prescaler designed for 4 / 5, DMP, P counter is 7, S counter is 2 bits. Therefore, the programmable divider can achieve more than the maximum frequency is 515.

1.2 4 / 5 prescaler structure

4 / 5 synchronous counter prescaler structure, the structure shown in Figure 2, the structure of the three SCL D flip-flop and two with non-door form. Mode signal divide ratio control signal, when the Mode is "1", the prescaler divide ratio is 5, when the Mode is "0", the prescaler divide ratio to 4. Since 4 / 5 prescaler directly work in the VCO output frequency is the highest frequency of the programmable divider part of the work, so this part of the circuit design of the main emphasis on speed, power consumption is the highest. This part of the circuit structure of the analog circuit SCL to achieve, SCL structure of the circuit by the switch turn-on of tail current logic level control to achieve the conversion, high speed of its work to meet the design requirements. D flip-flop by the clock anti-D with the two latches form, and in order to reduce gate delay to improve speed and lower power consumption, will be integrated with non-logic gate within the D flip-flop with the D and non-logic trigger circuit shown in Figure 3.

Figure 2 4 / 5 prescaler structure

Figure 3 Integration of the D flip-flop with non-logic circuits

1.3 programmable swallow counter and pulse counter design

Pulse swallow programmable counter counter P and S work in lower-band frequency divider, a simple structure to achieve the asynchronous frequency counter function. This part of the circuit is usually implemented in two ways: analog circuits and digital circuits, in the design of analog circuits based on SCL to achieve, as opposed to digital circuits although some static power consumption, but the circuit noise is low, process small size, the performance is good. Structure of the programmable divider shown in Figure 4.

Figure 4, the programmable divider structure

Which P counter is set in part by seven the number of functions with D flip-flop constituted; S counter part by two D flip-flop the same composition, the other including two with non-logic control gates constituted pre-feedback divider frequency ratio; testing and set the number of logic gates and by the 5 and 1 or door composition. D flip-flop and logic gates are simulated by the structure of the SCL-based circuit, a fully differential structure. S in the P counter and the counter, each D flip-flop to form a 2 divider, divider and then every 2 cascade. Detection and set the number of logic functions is to make the P counter and the counter S is set automatically after a few, this part of the design is very critical, direct impact on the entire operating frequency divider, in this paper proposes a new detection and set the number of logic to improve the performance of the divider and the operating frequency. The following test set by comparing the number of traditional logic and improved detection and set the number of logic to explain the advantages of the improved.

1.3.1 Detection and set the number of traditional logic design

In the traditional dual-mode divider based on the design of a programmable divider, is a P counter counts down to 0 testing, and through certain to produce a set number of sequential logic enable signal enables the counter and S P counter set number. The detection and set the number of logic circuit shown in Figure 5, when the P counter counts down to 0, P D flip-flop for each counter-ended output Qn is 1, then the logic gate output with cascade transitions from 0 to 1, forming a rising edge (as a test signal). As the rising edge D flip-flop with reset function (DFF-RE) clock input, DFF-RE reset Duanyou 4 / 5 prescaler output control, that is, in the strict timing control, when detected, the counter P counting down to 0, generate a rising edge of the signal, then DFF-RE Open, the rising edge of the signal makes the DFF-RE output from 0 to 1, DFF-RE after some time off, so the formation of a set number of pulses, so Counter re-set number.

Figure 5 detects the number of logic 0 is set programmable divider

In this structure, the number of testing and set the whole process of the input signal must be completed within one cycle, thus limiting the operating frequency divider. The following test set by the number of the traditional logic of the timing analysis to illustrate the higher frequency when the input pulse out of the phenomenon, and its timing diagram shown in Figure 6, in which the divider of the input signal fin, fp 4 / 5 frequency output signal, as DFF-RE of the reset signal, Ld0 counter to 0 for the P test when the combinational logic circuit output signal, Ld is set to the number of enable signal, that is, the output signal of DFF-RE, Mode is Control 4 / 5 prescaler number of signals. The figure shows, the counter counts down to the P 0, the detection logic outputs a pulse (Ld0), counting from the P to 0 to generate a pulse signal detection gate delay of t0, the number of detected pulses to the home pulse (Ld) of the delayed time t1, Mode signal generation delay t2. Mode signal from the detected so the total delay time of rising t0 + t1 + t2, if the total delay time is greater than an input signal cycle, shown in Figure 6, Mode signal control of the 4 / 5 prescaler The frequency of the 2 into 1 5 5 1 4 frequency and the frequency, which pulses the phenomenon out there, eventually leading to the divide ratio error.

Figure 6, 0 errors detected timing analysis graph

1.3.2 improved detection and set the number of logic design

According to the system design requirements, the work of the highest frequency divider should reach 4.0 GHz, based on the traditional crossover detection logic is difficult to set the number of stable jobs at this frequency. Therefore, the design uses in the P counter is counting down to a test, through a certain timing control, when the P counter number is set to 0, so that the process of testing and set the number of input pulse in two cycles to complete, compared to count to 0 crossover detection, the working frequency can be increased by 2 times. The following specific set of Improved detection of the number of logical sequence. Set in the number of improved detection logic, shown in Figure 4, when P when the counter counts down to 0000001, P counter DFF3 ~ DFF7 the QN-ended output is 1, so AND0 output from 0 to 1, AND0 output DFF-RE reverse signal as reset signal terminal, and 4 / 5 divider output signal as DFF-RE inverting the clock signal. The detection and set the number of sequential logic diagram shown in Figure 7, when detected after P counts to 1, DFF-RE will be open, set the number of delayed pulses as t0, Mode signal generation delay of t1, so the detected Mode rising edge of the total signal delay t1 + t2, compared to Figure 6, one less gate delay, so 4 / 5 prescaler for the correct frequency of 2 times 5 minutes, avoiding the phenomenon of pulse out. Set of improved detection from the number of logical sequence analysis, the improved design makes programmable divider can operate at higher frequencies.

Figure 7, when the test is set to 1 the number of logic timing diagram

2 circuit layout design and simulation results

2.1 programmable divider layout

The territory of the overall programmable divider shown in Figure 8, the divider circuit is differential in the structure of each unit, you need to take into account the matching design of the device, while the rational distribution of the cell circuit needs to reduce the critical the connection path delay and layout area savings.

Figure 8, the map of the overall programmable divider

2.2 programmable divider simulation results

Simulation results of this paper is to layout parasitic extraction was conducted after the results obtained after the simulation. Maximum operating frequency of up to 4.5 GHz, the operating voltage power consumption is about 2.5 V under 19 mW. Figure 9 is in the 4.5 GHz frequency, the 4 / 5 after the simulation waveform divider. Figure 10 is a programmable divider at 4.5 GHz, the frequency division ratio of 450, P counter preset number of 112, S 2, the counter preset number of working waveform. Can be seen from the figure the 4.5 GHz programmable divider can be achieved in the correct frequency.

Figure 9 4 / 5 prescaler simulation results

450 Figure 10 editable frequency divider simulation results

3 Conclusion

For RF band frequency synthesizer, the divider has become a bottleneck restricting the speed loop. Based on the structure of the pulse swallow programmable divider of the number of logic circuit testing and home improvements, making the divider of the work speed can reach 4.5 GHz, to meet the multi-standard mobile digital TV receiver tuner chip design targets At the same time as the width of the divider with continuous divide ratio, it can also be applied to other RF wireless transceiver chip. At the same time, the use of SCL structure analog circuit chip, the programmable divider allows smaller, about 106 m 187m.

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