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The motor drive is connected to the source of the design method of PWM

In Electronic Infomation Category: T | on April 15,2011

How to PWM logic signal source connected to the battery-powered motor drive is a difficult problem we face. This article describes the PWM motor drive connected to the source of design, including the relevant equations and SMBJ17CA datasheet and component selection guide. The method used in the circuit including the accuracy and SMBJ17CA price and sensitivity analysis with an example.

The motor drive is connected to the PWM source

LM4570 is an eccentric rotating mass (ERM) and SMBJ17CA suppliers and linear resonant excitation (LRA) motor driver IC, for mobile phones and other portable media devices. This paper details the design of the LM4570 PWM source connected to the set procedure. Although the LRA

bipolar motor is AC waveform to drive close to the resonant frequency of LRA, but the ERM motor driven mainly by the DC voltage. As required by DC, which may not appear AC coupling capacitor and the input of driver IC series.

Design and PWM driver IC connected to the interface requires a lot of mathematical knowledge in order to ensure proper operation.

First step in the design of the circuits is to determine the required gain. PWM voltage source can provide the following levels:

Type 1:


Where VIN (PEAK) is the PWM single-ended source can provide peak output voltage, VLOGIC is the PWM logic high voltage. If the PWM source can reach 0% and 100% duty cycle, use the type 1. If the PWM Yuanda less than 0% and 100% duty cycle, use the type 1a, because the need for a corresponding decrease in accordance with the type VIN (PEAK):

Type 1a:


Which DC (MAX) and DC (MIN) are the source of the maximum and minimum PWM duty cycle. Please use DC (MAX) or DC (MIN) makes it possible to produce the smallest VIN (PEAK) key to ensure symmetrical swing. The next step is to determine the flow through the ERM

desired peak output voltage of the motor VOUT (PEAK). In order to achieve all of the battery voltage is the same operation, you can set this value to 3V or lower, or they set it to 4.2V so that the battery is fully charged condition to obtain the maximum speed driven. ERM must follow the specifications to test the motor peak output voltage to ensure that the amplitude and duration of no more than specified by the manufacturer ERM motor specifications. We can use the VOUT (PEAK) and VIN (PEAK) to calculate the system gain:

Equation 2:


Where "gain (Gain)" is a single-ended PWM from the source to the bridge-tied load (BTL) output of the gain amplifier.

Required on the circuit in Figure 1 show that the BTL gain of the output of 2X gain corrections, resistor can be calculated by the following formula:

Type 3:


Easiest way is to RF elected 200k, and then calculate the RG1 and RG2 and. The RG is divided into two resistors is to allow adding a bypass capacitor CF, in order to form a first-order low-pass filter. The low-pass filter to prevent the contents from the high frequency PWM signal from the amplifier and the ERM motors radiation. RG1 and RG2 will be chosen the same value, you can use them and, and by type to calculate the required gain of 3. Low-pass filter cutoff frequency can be calculated by the following formula:

Type 4:


F-3dB

which is a low-pass filter cutoff frequency, usually set to 2kHz to 5kHz.

The design of the circuits final step is to increase the bias for the REF2 correct (see Figure 1). Required to do so is due to the average DC level PWM sources (half VLOGIC) is different from the average of the output DC level (half VBATTERY change value). Select the resistor R1 in Figure 1 and R2 to complete this operation. Please note, REF1 pin Thevenin (Thevenin) impedance of about 10k, so we will select R2 approximately equal to 200k, so that the load effect can be ignored. Bias formula is as follows:

Type 5:



Figure 1: interface with LM4570 PWM motor drives

Which is parallel R1 R1A and R1B (two resistors to form the partial pressure) the equivalent impedance. Similarly, if the duty cycle of PWM input is 50%, and the output and VDD / 2 balance, the voltage can be derived formula IN:

Type 6:


Obviously, type 5 and type 6 is actually the same in form, so we can find, just so that R2 is equal to RF, and to R1A and R1B can double the value for the RG. One advantage of using symmetric circuit is removed from the calculation of VDD Summations items, which makes this circuit is no longer sensitive to changes in battery voltage.

Formula in order to test these, we will use the example with the following parameters: VLOGIC = 1.5V, VOUT (PEAK) = 3.0V

For the above values, we need to "gain" to 4. 200k will be selected and used RF to calculate the RG-type 3 is equal to 100k, or the RG1 and RG2 equal to 49.9k. Since these two parts are symmetrical, the 200k and R2 selected type 3 can be used again to calculate the R1 is equal to 100k, or R1A and R1B is equal to 200k. In order to estimate the circuit performance * we 0-100% duty cycle of the input of scan parameters, and will gradually increase the battery voltage from 3.0V to 3.6V, up to 4.2V. In addition, we use Monte Carlo (Monte Carlo) assay to determine the sensitivity and resistance (the results shown in Figure 2).


Figure 2: Simulation results

Shown in Figure 2, VO1 and VO2 between the two complementary outputs. Please note that the two signals at 50% duty cycle point or 0.75V on the input will always intersect at zero. Even when the battery voltage is within the scope of its changes available, but also in half the battery voltage at the intersection.

Simulation in Figure 2 is resistor tolerance of 1% of the Monte Carlo scans. Shown in the figure, each slightly wider alignment, which means that only produces negligible performance impact.

Shown in Figure 2, VO1 and VO2 between the two complementary outputs. Please note that the two signals at 50% duty cycle point or 0.75V on the input will always intersect at zero. Even when the battery voltage is within the scope of its changes available, but also in half the battery voltage at the intersection.

Simulation in Figure 2 is resistor tolerance of 1% of the Monte Carlo scans. Shown in the figure, each slightly wider alignment, which means that only produces negligible performance impact.

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