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TMS320C6713 controller based data acquisition system

In Electronic Infomation Category: T | on April 22,2011

Abstract: TMS320C6713 for the controller design and NC7ST32P5X datasheet and implementation of EMIF interface based data acquisition system. In fact, AD can be external data memory chip as an external device, by reading the memory data get in the way of data to be collected. Mainly from the introduction of hardware and NC7ST32P5X price and software both use EMIF interface, the final experimental results show that fully meet the requirements of the data collected, based on EMIF interface to achieve data acquisition system, and NC7ST32P5X suppliers and also a brief description of the TMS320C6713s EMIF interface to a simple application.

Recent years, with the development of micro-controller, all kinds of industrial control products to the needs of modern digital controllers is also growing. This in turn contributed to the modern large scale integrated circuit and the continuous development of micro-controller, while the operating frequency of various types of digital processor is also faster and faster, such as TIs TMS320C6000 controllers can achieve 200 MHz. In order to support a variety of seamless connection between the external memory, TMS320C6000 series of processing chips joined the External Memory Interface (The External Memory Interface, EMIF). This design mainly based on TIs TMS320C6713 floating-point core chip as the main controller. Floating-point DSP TMS320C6713

1 Introduction

TMS320C6713 is a high performance floating point DSP, its working frequency up to 200 MHz, the single instruction execution cycle is only 5 ns, with a strong fixed-point floating-point computing power, computational speed of up to 1 600MIPS / 1 200MFLOPS.

TMS320C6713 processor consists of three main components: CPU core, memory and peripherals.

CPU contains eight functional units can operate in parallel; has two sets of registers, each register by the 32-bit registers 16. On-chip program memory bus width of 256 bit, desirable 8 per cycle 32-bit instructions. Peripherals including the expansion of the direct memory access (EDMA), low-power, external memory interface (EMIF), serial port, McBSP Interface, IIC interfaces and timers. TMS320C6713 functional block diagram shown in Figure 1.

Figure 1 TMS320C6713 Functional Block Diagram

Summarize a whole, TMS320C6713 has the following characteristics:

1) high-performance floating-point DSP, clocked up to 200 MHz, speed of operation up to 1600 MIPS;

2) very long instruction word (VLIW) DSP core: 8 independent functional units (6 multiplier accumulator and 2), 32 32 bit general purpose register storage loading structure, can greatly reduce the instruction code package;

3) L1/L2 Memory Architecture: 4 KB L1P cache, 4 KB L1D Data Cache: 256 KB L2 memory: 64 K bytes which can be configured as cache or memory, 192 K bytes of memory unity of the image can be flexible positioned for the program / data space;

4) 32-bit external memory interface (EMIF): asynchronous memory interface can be configured to expand SRAM and E2PROM; synchronous memory interface can be configured, scalable SDRAM and SBSRAM; 512 MB of addressable external memory space;

5) 16-bit HPI interface to any CPU can access the addressable space;

6) 2 Ge serial multi-channel buffer (McBSP);

7) 2 I2C-bus master / slave mode interface;

8) built-in flexibility of the PLL phase-locked clock circuit;

9) support the 1EEE-1149.1 (JTAG) boundary scan interface; 10) 16 GPIO interface.

Comparison with other DSP, TMS320C6713 main advantage is to run fast, convenient storage configuration, resource-rich, which gave the design of micro-controller is a big convenience.

2 EMIF Introduction

TMS320C6000 the EMIF interface, the external memory interface (The External Memory Interface), support the seamless interface to various external devices, including: pipelined synchronous burst SRAM (SBSRAM); asynchronous DRAM (SDRAM); asynchronous devices, including SIAM, ROM, and FIFO, etc.; external shared memory.

Simply, EMIF interfaces to the equivalent of a configurable bus interface, its interface signal lines above the basic cover a variety of memory (SRAM, Flash RAM, DDR-RAM, etc.) to read and write interface signals. Register through the appropriate software configuration, you can make EMIF interface, and design work on the use of external memory interfaces to match the fixed form. But the other difference is that the fixed interfaces, EMIF interface to read and write timing of the high and low level of hold time is set by the register.

Following the design used for this example in detail about TMS320C6713 EMIF. TMS320C6713 De EMIF requester can handle the following two external bus request: on-chip enhanced direct memory access EDMA controller; external shared storage device controller.

Figure 2 is a diagram of TMS320C6713 the EMIF interface signals.

Figure 2 TMS320C6713 the EMIF interface signals diagram

In Figure 2, ECLKIN signal is provided by the system to an external clock source. ECLKOUT signal is generated internally (based on ECLKIN), all EMIF interfaces with the docking of the memory controller to work under the ECLKOUT. SBSRAM the interface, SDRAM interface, and asynchronous interfaces combined multiplexed signal. CE1 Chip Select space here to support all of the 3 memory interface. TMS320C6713

Table 1 lists the EMIF memory mapped registers. By setting these registers, the EMIF configuration either into different types, different bit wide bus interface, and timing can be configured to read and write speed of the bus. Because of this advantage EMIF interface, EMIF interface designers using the integrated control chip, whether to expand the external storage device, or external devices using EMIF interface to read, and its difficulty is greatly reduced. This is to some extent with the EMIF interface also makes high-speed control core (TMS320C6000 series DSP) in the future can be more widely used.

Table 1 TMS320C6713 the EMIF memory mapped registers

3 Hardware Design and Implementation

3.1 Requirements Analysis

The main task is to complete the hardware design of the main circuit voltage, current collection, specific requirements shown in Table 2.

Table 2 main requirements

3.2 Hardware Design TMS320C6713

Figure 3 shows the block diagram of major functional peripheral.

Figure 3 TMS320C6713 peripheral functional block diagram of the main

Shown in Figure 3, the design of peripheral devices include: dual-port RAM, for use with fixed-point DSP core chip (eg TMS320F2812) exchange of data; Boot Flash, when the program is larger than 192 KB, used to store Start the program; SDRAM, as part of the program storage medium run; CPLD, for the logical extension; AD7865, used to collect voltage and current, real-time data.

AD7865 is a high speed, low power, four-channel simultaneous sampling 14-bit A / D converter chip, the chip has a 2.4s successive approximation A / D converter, four track / hold amplifier , internal 2.5V reference voltage, while also integrated on-chip clock oscillator and a high-speed parallel interface. AD7865 can greatly simplify the hardware circuit design. AD574 conversion time is 25s, while the AD7865 to complete four-channel signal at the same conversion, only needs 100 s. AD7865 internal 4-channel input signal is sampled synchronous sampling, simply send a pulse of the sampling start signal, the chip will automatically complete the sampling, approximation, and store data to a chip-specific registers, etc., single sampling rate 350 KSPS, Four simultaneous acquisition time 100 kHz. Can be set according to design requirements

conditioning circuit magnification of 2 times (inverting amplifier), the actual value of A / D sampling by the relationship between the value of equation (1) said.

Actual value = samples / 213x10 / (-2) sensor factor (1) If the sample is positive

available when equation (1), or to be the first to complement treatment.

AD7865 front-end conditioning circuit shown in Figure 4.

Figure 4 AD7865 front-end conditioning circuit

AD7865 external connection circuit shown in Figure 5.

Figure 5 AD7865 external connection diagram

TMS320C6713 the EMIF interface to the signal line can EMIF interface diagram (Figure 2) connection. Note that here the signal line pull, pull-down and limit the signal line and other measures. Designed in accordance with the following principles: 1) address lines and data lines and control lines to exit 33 resistor in series to achieve the effect of limiting; 2) for some sensitive signals (eg, chip select / CEx signal, to maintain the signal / HOLD, etc.) in the default state level, should pull through and down to find out. Under normal circumstances, with a 10 k pull-up resistor resistor resistor with a 1 k pull-down resistor.

CPLDs main function is to achieve the logical extension, in this design, CPLDs main work is in the DSP6713 and multi-chip AD7865 chip signal between the resolution and transmission. ALTERA CPLD chip is selected the companys EPM570, the chip compared to other terms of the same type of CPLD, simple configuration, storage capacity and cheaper. The external circuit is relatively simple, can refer to the ALTERA company on the chip pins menu, in the not to repeat them.

4 software and part of the flow chart

4.1 EMIF interface configuration to achieve

TMS320C6713 EMIF interface data to achieve the first condition to read EMIF interface is configured properly register in order to meet the design requirements. The design will CE3

AD as an external address space, so here you need to configure the EMIF registers the main key is the global control register GBLCTL and CE3 space control registers. Of course, to properly configure the EMIF interface, must be properly configured TMS320C6713 phase-locked loop (PLL) register is not specified here. Configuration TMS320C6713 PLL (PLL) register the future, they can configure the EMIF control registers of the bus a few. The design of the main register in the specific configuration of several parameters are as follows:

Used in this design approach for the 32-bit EMIF interface, asynchronous interface (MTYPE = 0010b). Although the AD7865 is a 14-bit MD converter is configured to 16 bit wide interface mode can be, but in fact, due to internal data processing order to calculate the convenience of using a 32-bit data, typically 32 bits wide, in the external reads, if the 16-bit width, then a read

Take the bus to match the data length, will be read twice to send a continuous read signal, which to some extent, although the faster A / D reading speed, but in the subsequent data processing operations and the need for more more time, so weigh all factors, the 32-bit wide asynchronous interface mode.

4.2 to achieve A / D conversion and reading data

Actual use, AD7865 only need to start the conversion and ADCONV given chip select signal. And it read in two ways:

1) read the data conversion process, which converted all the way to read all the way;

2) the signals of all channels after the conversion is complete in order to read all the channel data.

Two ways to read the main difference is: the first one kind of read speed, but the timing requirements of high complexity of the hardware connections, increasing the difficulty of hardware and software design; and section 2 read speed is relatively slow, But the timing insensitive, software and hardware design is relatively simple. Taking into account the reliability of the system, while less capable CPLD timing to complete, so the design uses the first 2 to read way.

The actual use of the A / D conversion and reading the main flow shown in Figure 6.

sample flow chart in Figure 6

5 measurement results

Auxiliary controller design this after the completion of hardware and software testing.

Used mainly for testing DC power supplies, test consists of forward voltage, reverse voltage (ie, that the sensor factor is 1.) The results in Table 3. Table shows test results from the error is less than 1%, in full compliance with design requirements.

Table 3 the results of the test voltage and calculated

6 Conclusion

From the measured data and calculated results shows that the controller, the design is completed based on EMIF interface data acquisition system design task. The data collected by the system errors are small, to meet the needs of various projects. Online debugging. Can be seen in the actual sampling process, the sampled data is a value in the vicinity of volatility, in some degree of demand for real-time data is not very high, while demand for higher data accuracy of the occasion, can strike over a certain period average value of short sampling methods to improve data accuracy. Moreover, since the controller selects a high performance TMS320C6000 series DSP, its still a great performance and resource availability. Data collection system is complete, high-speed high-precision calculation of power system parameters, such as three-phase voltage / current and phase, active power and reactive power, power factor and harmonic analysis calculations.

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