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Species based on high-speed PCI bus interface PCD656 Design and Implementation

In Electronic Infomation Category: S | on April 14,2011

Modern radar signal processing with large volumes of data, real-time advanced features, and MC74HCU04ADR2 datasheet and determine the efficiency of bus transport system performance, the current widespread use of standardized PCI bus technology to upgrade the update. To speed up product development and MC74HCU04ADR2 price and reduce the design difficulty, there are two solutions: using a common PCI chip or IP core. PCI chip such as the commonly used PCD054, PCD052, etc. Although the performance is stable, easy to use, but they apply only to 33 MHz, 32-bit bus interface, the design and MC74HCU04ADR2 suppliers and application by the timing of efficiency, the bus transmission speed of approximately stable at 70 MB s- 1; use the IP core, although compatible with 66 Hz, 64-bit bus and saves board space, but its high price is not conducive to promoting the use of universities and SMEs. The PCI9656 for 66 MHz, 64-bit PCI bus, the bus has become the mainstream of the development of components, making the bus transfer speeds of up to 150 MB s-1 or even higher.

This paper, efficient PCI chip and FPGA design of a 64-bit bus interface circuit transmission, the transmission speeds of up to 212 MB s-1, the bus transfer rate than in the past have been greatly improved to meet the current high-speed data transmission system requirements.

1 PCI bus interface architecture

The system constituted by the PCI9656 and the FPGA, the system block diagram shown in Figure 1. When the host read and write operations initiated in response to its need to operate PCI9656, and the corresponding command is sent to processing FPGA, FPGA for processing data and commands through the PCI9656 will be back to host. PCI9656 communication with the host requires a corresponding device driver support, and FPGA response to host commands you need to configure the local timing. Therefore, the design of the main work for the device driver development and FPGA design of local timing.

overall transmission system block diagram of Figure 1 Performance

2 PCI9656 Overview PLX

PCI9656 is compatible with the company introduced a 32-bit and 64-bit PCI bus standard bridge chip, the use of PLX data pipeline (Data Pipe Architecture), with the internal DMA controller, programmable from the main mode of transmission and Mode transmission; internal PCI device priority decision to support the external seven external master; by local interrupt signal LINTi and LINTo generate a PCI interrupt INTA; local clock independent of the PCI clock; support the bit width is 8 bits, 16 bit and 32-bit 66, MHz local bus. PCI9656 PCI9054 register and register-compatible, can easily be 32-bit PCI bus-based 64-bit PCI bus-based software migration.

PCI 9656 has six independent data channels, respectively, support the Direct Master, Direct Slave and DMA mode data transfer function.

(1) Direct Master mode. For the local bus to PCI (CompactPCI) data transfer, the master device in the local bus terminal. 16 QWord (128 Byte) and 32 QWords (256Byte) of each applied to the data FIFO read and write access.

(2) Direct Slave mode. For PCI (CompactPCI) to the local bus data transfer, the master device in the PCI side. 16QWords (128 Byte) and 32 QWords (256 Byte) for each applied to the data FIFO read and write access.

(3) DMA mode. PCI9656 DMA transfer is also PCI and local bus master devices, PCI 9656 has two DMA channels (Channel 0, Channel 1), each channel consists of a DMA controller and 32 QWords (256 Byte) composed of bi-directional FIFO. The DMA mode of conventional block mode (Block Mode), distribution model (Scatter / Gather Mode) and command mode (Demand Mode).

The local bus terminal, depending on the processor PCI9656 has 3 modes of operation.

(1) M mode. Motorola 32 bit processor support, providing a direct connection with MPC850/860 PowerQUICC interface.

(2) C mode. General pattern for most processors, such as the commonly used FPGA, the design used in this mode.

(3) J model. A similar pattern with C, but the address lines and data lines multiplexed.

3 bus device driver development

In the Windows environment, PCI device driver development, there are two main models, namely, WinDriver and WDM. The design uses the WDM driver model. PCI WDM device driver developers need to deal with: the hardware access, interrupt handling and DMA transfer three aspects.

3.1 hardware access

X86 processors have two separate maps of space: I / O space and memory, I / O space only through the I / O instructions to access, KIoRange class encapsulates the I / O space operations command. For the design of the PCI device, you can instantiate KIoRange class of I / O space for appropriate action.

For the PCI device can use KMemoryRange class corresponding to the memory operation, the specific operation and KIoRange class of I / O space operations similar.

3.2 interrupt handling

Driver class to use KInterrupt the handling of the interrupt operation, including the initialization of the interrupt, an interrupt service routine is connected to an interrupt and the lifting of its connections.

Interrupt service routine is not KInterrupt class member function, which is to reduce the interrupt latency time. Need to interrupt service routine interrupt handling and deferred procedure call routine, the interrupt service routine, first determine whether the interrupt is generated by their equipment, if not, it returns False; and if so, request a deferred procedure call routine ( DPC).

3.3 DMA Transfer

PCI9656 way of using the DMA data transfer. DMA transfer needs to achieve three categories: KDmaAdapter, KDmaTransfer and KCommonDmaBuffer. Which, KDmaAdapter class is used to create a DMA adapter, it shows the DMA channel characteristics, such as bus width, the maximum number of single transmission, etc. Note that this device uses 64-bit bus width, it needs to be noted ; KDmaTransfer class is used to control DMA transfers, such as the transmission began, the number of bytes transferred, etc.; KCommonDmaBuffer class application system for the provision of public buffer. Specific DMA transfer settings are as follows

(1) instance of the three classes

OnDmaReady routine for transmission of the physical memory address and the number of bytes, and then set the appropriate DMA registers start DMA transfer. After the DMA transfer should be made m_CmxentTm-nsfer invalid and deleted. Specific processes shown in Figure 2.

Figure 2 DMA transfer process

4 local bus terminal design

This design, the local bus terminal with a C model. C mode, data transmission can be configured 3 ways: single-cycle mode (Single Cycle Mode), 4 word means (Brust-4 Mode) and continuous burst transfer mode (Continuous Mode), used in the design of a continuous burst mode can effectively increase the output efficiency.

PCI9656 local bus to the main equipment, always take the local bus, local bus side of the FPGA always respond PCI9656 operation. Using the PCI9656s DMA program transfer mode, the address is not required in the local decoding, so you can control on the PCI9656 signals simplified, PCI9656 local terminal main control signals are as follows

ADS #: a bus access start;

Blast #: bus end of the visit;

LW / R #: read-write control signal;

Ready #: ready signal from the device, the effective conduct of said bus access;

LHOLD: PCI9656 local bus occupation signal applications;

LHOLDA: take the local bus acknowledge signal;

Wait #: master to suspend signal transmission;

EOT #: data abort signal for the FIFO overflow interrupt or the space-time data transmission;

Lint #: bus-side for the cause CompaetPCI interrupt signal;

LRST #: local bus reset signal;

CCS #: configuration register select signal.

DMA transfer process in the signal can be simplified as the main concern: ADS #, Blast #, LW / R #, Ready #, LHOLD, LHOLDA, shown in Figure 3.

Figure 3 PCI local bus control timing

Figure 3, lclk for the local bus clock, when the PCI9656 to initiate a DMA operation, the first signal sent lhold applying for local bus, local bus free if you send lholda FPGA signal response PCI9656, then the effective ads_n PCI bus signals to show transmission began, FPGA to ready_n effective bus transfer is in progress to show, this time local data transmission through the local data lines to the PCI bus, or the data from the PCI bus to the local logic. PCI to the end of a transmission signal is valid and to lhold blast_n signal is invalid, then so lholda signal and ready_n FPGA signal is invalid, a DMA transfer is complete. If the DMA read transfer signal is lwr down, if the write operation is pulled.

Local Bus Width 32-bit, so local bus theoretical speed of 264MB s-1, because the efficiency of application and transmission of the existence of some invalid state, the current average rate of PCI bus to 212 MB s-1 to meet the current high-speed data collection, transmission on the bus transmission speed.

PCI9656 local bus designs to note blast_n timing signals indicate the effective clock cycle, the last burst transfer, this time ready_n signal is still valid, otherwise it will cause the bus to wait; in the normal read and write access to the CCS # signal should be set high Otherwise, bus access will point to the configuration space rather than memory or I / O space.

5 Conclusion

Achieved using PCI9656 and a high-speed FPGA PCI bus interface, a more comprehensive treatment of the local timing bus driver development and design process. This design improves the bus transfer rate, as high-speed data acquisition system to create the conditions.

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