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SPI bus characteristics, working methods and common error solutions

In Electronic Infomation Category: S | on April 13,2011


1.SPI Bus

SPI (serial peripheral interface, serial peripheral interface) bus technology Motorola has introduced a synchronous serial interface. It is used for CPU and NZT751 datasheet and various peripheral devices full-duplex, synchronous serial communication. It can be completed only four lines to MCU communication with a variety of peripheral devices, these four lines are: serial clock line (CSK), the host input / output data lines from the machine (MISO), master output / slave input data line (MOSI), active-low slave select line CS. When the SPI work, the data in the shift register bit by bit from the output pin (MOSI) output (high first), while from the input pin (MISO) data received by the displacement to the shift register (high first) . After sending a byte from the peripheral device to receive another byte of data into the shift register. One byte data transfer is complete is the essence of the exchange register two devices. SPI master clock signal (SCK) to transmit simultaneously. Typical system block diagram is shown below.

Figure 1 Typical system block diagram

2.SPI the main features of the bus

Full duplex;

Can be used as master or slave work;

Provides frequency programmable clock;

Sending end of the interrupt flag;

Write conflict protection;

. Bus competition protection.

3.SPI bus work

SPI bus, there are four ways of working, which is the most widely used and NZT751 price and SPI3 SPI0 mode (solid line):

Figure 2 SPI0 and NZT751 suppliers and SPI3 mode (solid line)

Sequence of four works were:

Figure 3, the four work timing Detailed


CPOL: Clock Polarity Select for the SPI bus is idle 0 is low, the SPI bus 1 idle is high

CPHA: Clock Phase Select, 0 transition in the first SCK edge sampling for 1 second at the edge SCK sampling

Work 1:

When CPHA = 0, CPOL = 0 Shi work in the way of an SPI bus. Data on the MISO pin in the first SPSCK along the transition on the line before, but in order to ensure the correct transmission, MOSI pin of the MSB bits must be synchronized SPSCK the first edge in the SPI transfer process, the first data line, and then synchronize the clock signal rising edge, SPI capture the receiver signal, the clock signal the end of a cycle (falling edge), the next data signal on the line, then repeat the process until a byte 8-bit signal transmission end.

Work 2:

When CPHA = 0, CPOL = 1 Shi SPI bus is operating in mode 2. The only difference with the former only at the falling edge of clock synchronization signal capture, data on the rising edge of a line nowadays.

Work 3:

When CPHA = 1, CPOL = 0 Shi SPI bus is operating in Mode 3. MISO MOSI pin on the pin and the MSB bits of data must be synchronized SPSCK the first edge in the SPI transfer process, synchronized clock signal in the beginning of the cycle (rising) data on the line, and then declined in the synchronous clock signal along the time, SPI receiver capture signal, the clock signal the end of a cycle (rising), the next data signal on the line, then repeat the process until a byte 8-bit signal transmission end.

Work 4:

When CPHA = 1, CPOL = 1 Shi SPI bus is operating in mode 4. The only difference with the former only when the synchronous clock signals rising edge signal capture, data on the falling edge of a line nowadays.

4.SPI bus common error

4.1 SPR configuration error

Device clock frequency from the master clock frequency is less than, if set too fast a rate of SCK will result in the received data is not correct (SPI interface, it is hard to judge whether the data received is correct, to the software treatment).

Overall speed by three factors: the primary master clock CLK, CLK from the clock from the device and the synchronous serial clock SCK, SCK which is divided Lord, CLK, CLK and CLK from the Lord is asynchronous. For SCK is error-free without omission from the device are detected, the clock CLK from the slave device must be fast enough. SCK CLK below to set the main frequency of the waveform 4 as an example, synchronous serial clock, master clock and slave clock relationship.

Figure 4 master-slave relationship between the clock and SCK

Shown in Figure 4, when T From Figure 5, when the T from TSCK / 2 = 2T the Lord, both in the clk_s not detect SCK rising edges have a low level, so that the device will be missing from a SCK. Phase in some conditions, even if the CLK lucky enough to be detected from the SCK low level, we can not guarantee to continue testing to the next SCK. As long as the omission of a SCK, serial data is equivalent to missing a bit, back to receive / send data to is wrong.

Figure 5 master-slave relationship between the clock and SCK

Based on the above analysis, SPR, and the relationship between master and slave clock than as listed in Table 1.

Table 1 SPR set-up and the ratio of clock cycles between master and slave relationship

Before transmitting data in accordance with Table 1 on the SPR set, SPR setting error can be completely avoided.

4.2 model error (MODF)

Model error indicates that the master-slave mode select pin SS of the connection settings and inconsistent.

Devices when operating in master mode (MSTR = 1), its chip select signal SS pin must be connected to high. In the process of sending data, the SS if it is low from the high jump at the falling edge of SS, SPI module will detect the model error, the location of the MODF 1, forcing the device into slave mode from the main mode ( main role MSTR = 0), clear the internal counter counter, and end the ongoing data transmission, as shown in Figure 6 (a) below.

From mode (MSTR = 0), in the absence of data transmission time, SS high indicates the device is not selected from the from the device does not work, MISO output impedance; in the data transmission process, the chip select signal SS must then low, and the SS transition is not allowed. If the SS high jump from the low, jumped in the SS of the edge, SPI module will detect the model error, clear the counter within the counter, and end the ongoing data transmission. Low until SS restore, re-enable SPEN = 1 when it is back to work, as shown in Figure 6 (b) below.

Figure 6 model error detection

4.3 overflow error (OVR)

Overflow error that continuous transmission of multiple data, the latter data covers the previous data generated errors.

Status flag SPIF that the data transfer is in progress, its data transfer has a greater impact. The SPIF effective master data register empty flag by the SPTE = 0 generated from the device is effective only by receipt of SPIF the first transition on SCK, and because the slave device and master device issued SPIF SCK is asynchronous, so the SPIF flag from the transmission device relative to the master device from the transmission of a certain Lord mark SPIF lag. Shown in Figure 7, the master sends two consecutive data when the device will likely result in the transmission from the master symbol and a data transfer under the symbol overlap (Fig. 7, dotted lines and shaded), the first received The data must be overwritten, and the second data transmit / receive are bound to go wrong, resulting in an overflow error.

Figure 7 overflow error

Waveform from the device through the analysis, counter = 8 after the first clock cycle, the data transfer has been completed last. The data has been received / sent the case is completed, counter = 8 the length of the state has no effect on the accuracy of the data, it can shorten the counter = 8 state in order to avoid the former and the latter SPIF SPIF overlap. Thus, from the hardware at this stage to avoid overflow errors.

However, if you work from a device or software is fast enough to deal with other things, the SPI interface, the data received the case has not yet been read, but also receives a new data overflow error still occurs. At this point, SPI interface, a data protection is not covered before, discard the new data received, set the overflow flag OVR = 1; other interrupt signals (if the interrupt enabled), the notice read data from the device in a timely manner.

4.4 offset error (OFST)

SPI interface to the general requirements of the work from the device first, and then master began to send data. Sometimes the device out in the main process of sending data from the device to start work, or SCK outside interference from the devices failed to accurately receive eight SCK. Shown in Figure 8, received from the device 8 is SCK is the master to send data SCK two adjacent main. At this time, the main device and from device SPIF SPIF will overlap, the data dislocation occurred, from the device to correct this if you do not, then the data receiving / sending the wrong has been to continue.

Figure 8 offset error

In a data transmission process, SPR is not allowed to change, that SCK is uniform, can be seen from Figure 5, received from the device 8 SCK is not uniform, they belong to two data, so you can calculate the time SCK duty cycle to determine whether there has been offset error. The analysis, when the SCK = 1 the normal number of clock cycles when the values ??of n satisfy the following relationship:

But is asynchronous between master and slave clock, and after rounding, so normal when SCK = 1 clock cycle when the count value COUNT should satisfy:

Example, in Figure 5, COUNT maximum COUNT (max) = 2 or 1, can be considered normal. But there COUNT (max) = 8, you can determine the offset error occurred. In practical design, the first record of a Lower Dir COUNT (max) value, if the latter has emerged with the record value of more than a difference of 1, COUNT (max) occurs, we know that there are offset errors OFST occurred. SPI Interface in the "uneven" place that SPIF = 1, then wait for the next data for the first SCK. COUNT the number of bits which is fixed at eight, in order to avoid the overflow re-start counting from the 00H, when the count reaches ffH stop counting.

4.5 Other errors

Set incorrectly, or outside interference, data transmission errors will inevitably occur, or sometimes the software to determine the type of error is unclear, there must be a way to force the SPI interface to recover from the error state. SPI does not work at that time SPEN = 0, remove almost all of the internal SPI module state (except for special register.) If the software in the receiving data, the data can be found an error, no matter what mistakes, SPI can be forced to stop work, re-transmit data. For example, in offset error (OFST), if SPR2, SPR1 and SPR0 appropriately set, you can also make SCK look more "uniform." SPI interface hardware itself can not detect an error, if the user software to find errors, then you can stop the SPI transmission of the work force, so you can avoid the error has been sustained.

In the application, if the requirements of the higher accuracy of the data, in addition to the software to meet the SPI interface timing requirements, the software needed to make appropriate treatment.

5. Design SPI bus controller

Current project with the SPI bus interface FLASH memory to store image data. The SPI FLASH bus frequency up to 66M, but the MCU low frequency oscillator frequency 7.3728M, SPI frequency the maximum frequency is 1 / 2. 320 * 240 * 16 for the image read time of 333ms, but also neglected to wait for SPI transfer is complete, write memory, address and other coordinates set time. Actual test is about 1s. A great GUI design bottleneck. As TFT-driven FPGA design their own, resources are still margin, decided to SPI controller (master) and write some logic into the FPGA image using the hardware to complete.

First exposure to the SCK is the SPI clock rate problem. FPGA frequency is 48M, not using PLL. Whether this frequency as the SCK frequency? To know all the MCU provides a maximum frequency of the SPI frequency of 1 / 2! Why? Checked and found some information, SPI receive data from the machine not to SCK is the clock, but the frequency of the clock on the SCK and MISO is sampled by the sampling theory that SCK is not greater than 1 / 2 frequency, but also have a master MCU to provide the maximum frequency is 1 / 2 frequency, the maximum slaver frequency is 1 / 4 frequency. FPGA in the host can be achieved only as the same frequency as the frequency of the SCK it? ? Looks like the answer is yes! But Im still a bit worried, with the combination of logic control a larger burr SCK will not affect the stability of the system it?

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