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PicoBlaze soft core based on the design of TFT liquid crystal display control

In Electronic Infomation Category: P | on April 26,2011

TFT liquid crystal display (LCD) with low power consumption, small size, low voltage, long life, you can display text and ADS1100A2IDBVT datasheet and color images of complex, etc., in embedded devices has been widely used as human important way to interact. But the TFT liquid crystal display driver with a large amount of data, taking pin number and ADS1100A2IDBVT price and other characteristics, using traditional MCU-driven approach will not only spend a lot of system uptime, reduce system efficiency, but also take up a lot of I / O pins. For this, we propose a soft-core PicoBlaze based TFT LCD display control program, the ability to easily implement FPGA on the TFT LCD display control, with a strong versatility and ADS1100A2IDBVT suppliers and practicality.

1 PicoBlaze Architecture

8-bit embedded processor PicoBlaze is for the Virtex series of Xilinx, FPGA, Spartan series of FPGA and CPLD design CoolRunnerII series of soft-core embedded processor with high efficiency, less resource, etc., can be easily embedded into the hardware system design, implementation and seamless connection to other functional modules. PicoBlage Spartan series FPGA using only 96 Slice, 12.5% ??occupied XC3S50 device resources, take XC3S5000 device is less than 0.3% of the resources; with up to 44 ~ 100 MIPS instruction execution speed, depending on the selected specific speed FPGA series and device speed grade.

PicoBlaze 8-bit embedded processor provides a rich and flexible I / O port, and its peripherals can also be user configured to meet various system design requirements. As PicoB-laze provides a comprehensive HDL code can be easily ported to future FPGA architectures, so nothing to worry about out of the current difficulty in using the device to seek alternative products. In addition, PicoBlaze is fully integrated in the FPGA, reducing board space and design * fee.

Shown in Figure 1, PicoBlaze microprocessor mainly by the following elements: 16 8-bit general purpose registers; 1 KB program memory; 8-bit arithmetic logic unit, with CARRY and ZERO flags; 64 words section of the internal buffer RAM; 256 input and 256 output ports for easy expansion of applications; interrupt control unit.


Figure 1 PicoBlaze microprocessor structure

2 TFT LCD module

TFT LCD module is 320 240 pixels, 26 million color-color graphic dot matrix LCD can display numbers, characters, etc., can also display Chinese characters and arbitrary graphics. The module control chip SSD1289, and external connection is only 16-bit data lines, five control lines and power supply. LCD Module pin functions as listed in Table 1. TFT LCD modules to meet the standards of 8080 to read and write timing sequence in parallel, FPGA as long as these data lines and control lines in accordance with the appropriate timing for read and write, you can realize the display control module.

Table 1 LCD Module pin functions


3 hardware and software design

3.1 PicoBlaze assembler design

TFT LCD module built the SSD1289 controller chip, and its read and write timing to meet the 8080 standard parallel timing, therefore, the design of the PicoBlaze program to simulate the read-write timing can be realized on the TFT LCD module control. To read and write by software parallel timing simulation of 8080, there are two key technologies: one is the port to control the high-low; the other is to write software delay routine.

Level control of the port can be easily implemented through the OUTPUT command. For example:


Port can output data to the LCD_DATA_H 0xFF.

PieoBlaze did not provide the appropriate bit manipulation instructions, so the bit of PieoBlaze port operations can be achieved through the following procedure:


The program implements

the bit0 of LCD_CTRL_PORT be set to "1" and "0" operation, without affecting other bits. Every time before the output port, the port status is read from the register sF; and each output port is completed, save the current port status register in the sF.

Software delay routine can loop through to implementation. PicoBlaze instructions are all two-cycle instruction, when the system operating frequency is 50 MHz, the execution time of each instruction is 40 ns. Therefore, by calling the following routine can be realized 1s delay:


Which, delay_lus_constant = (clock_rate-6) / 4, where clock_rate 50. To achieve the port bit operating and software delay functions, the timing can be prepared in accordance with 8080 parallel send commands to read and write subroutines. The code is as follows:


3.2 PicoBlaze logical interface with the FPGA

PicoBlaze FPGA logic interfaces with the FPGA logic design, mainly in cases of PicoBlaze units, will be connected with the program ROM, and complete input and output ports of the latch decoder. The interface diagram shown in Figure 2.


Figure 2 Interface Schematic

PicoBlaze assembler KCPSM3.exe compiled by the assembler, to fill the code formed by the BLOCK RAM program ROM, in the FPGA logic design, the PicoBlaze program ROM and the corresponding pins of the module that KCPSM3 be. Latch decoding unit in each active clock edge, in WRITE_STROBE enable decoding under the control of PORT_ID and OUT_PORT latched on to the appropriate data register. The design includes three ports, namely, the high 8 bits of data lines DATA_H, the lower 8 bits DATA_L data lines and control lines CTRL, CTRL to bit0 ~ bit4 which represent the RS, RD, RESET, WR and CS.

Done in the FPGA logic and related PieoBlaze the case of the logical design, you can use the Xilinx ISE development tools, integrated comprehensive, implementation, and download validation. Comprehensive results show that the design takes up a total of 102 units Slice and a RAMBl6S, only XC2VP30-7FF896 total number and BRAM units Slice 1%. Finally, the generated bit stream into Xilinx XUP Virtex-II PRO development board for verification. The results show that the TFT liquid crystal display correctly drive a single species or variety of colors to achieve the expected goals. After calculation, when the system clock is 50 MHz, the full-screen refresh takes about 55.4 ms, with high real time. If the system clock up to 100 MHz, you can further speed up the refresh rate.

Conclusion

This PicoBlaze soft-core-based design of TFT liquid crystal display control program, has been in XilinxXUP Virtex-II PRO development board is verified, and achieved good results. It can be seen through the design, PicoBlaze is a powerful, flexible 8-bit embedded soft core processor can be used to implement the complex non-critical timing control functions, timing and other critical data path functions you need to FPGA logic implementation, the two combine to make the system more convenient and flexible.

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