Category:
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
0
1
2
3
4
5
6
7
8
9
Position:IcFull.com » IC Electronic information » Category: M

IC Electronic information

Multi-rate QC-LDPC decoder design and implementation

In Electronic Infomation Category: M | on April 26,2011

Abstract: The low-density parity check (LDPC) is the most effective means of error control, and PI5C3257QX datasheet and one quasi-cyclic LDPC codes (QC-LDPC) the most widely used. Presents a general multi-rate QC-LDPC decoder design and PI5C3257QX price and FPGA implementation and PI5C3257QX suppliers and test on completion. Test results show that the multi-rate decoder in the resource consumption rate is not more than two kinds of resources and the decoder can effectively support the premise of at least 3 rate; and working the clock at 110 MHZ, fixed number of iterations 16 times the throughput of the decoder can keep the 110 Mb / s or more.

0 Introduction

LDPC codes was first proposed in 1962 by Gallager, can be viewed as a sparse parity check matrix of linear block codes. Mackay and Neal found that since the performance of LDPC codes is very close to the Shannon limit later, LDPC codes more and more attention. Based on quasi-cyclic LDPC (QC-LDPC) codes structural features, a support multiple rate QC-LDPC decoder design, and design and implement a real-time adaptive array to support three different general QC H -LDPC decoder.

1 QC-LDPC codes Introduction

QC-LDPC code is a check matrix Hqc cycle replacement of c t matrices, where c, t are integers, and c

2 decoding Introduction

Here decoder designed mainly based on the offset value of the soft-decision minimum and algorithms. Offset the minimum and the algorithm is the smallest sum-product algorithm and improved algorithm based on and comes with a low decoding complexity and excellent performance characteristics. In order to better describe the algorithm, first define some symbols.

L (ci) represents the input variable node decoder soft information on the original i, L (rji) said that the check node j to variable node i to pass information, L (q ij) that pass from the variable node i check node j of the information. The ij, i j significance as shown in Equation 1:


Specific algorithm steps are as follows:

Original initialization code word probability information.


Step 1, the probability of check node update information (CNU, Check NodeUpdate).


Step 2, the probability of the node updates the information (VNU, Variable NodeUpdate).


Also calculated:


LQ the hard decision, if () 0 i LQ>, otherwise the decision is 0 to 1. CHT is calculated to 0, or has reached the set maximum number of iterations, step 3, if it is transferred, or transferred in step 1.

Step 3, the output verdict.

The simulation, the paper identified the decoder input point of the program are as follows: Quantitative bit wide for the 6 bit, which said 3 bit integer bit, 2 bit that decimal places.

3 multi-rate LDPC decoder design

First consider the following 3 QC-LDPC code word as a reference, code length 8 064bit, rate was 7 / 8, 3 / 4, 1 / 2. Among them, the different bit rate required for minimum and optimum decoding algorithm offset ((3) the offset value) obtained by the simulation, were 1, 0.7, 0.5. The QC-LDPC code pattern used in the expansion factor is 112.

Text LDPC decoder implemented in some parallel decoding structure based on the input and output decoder for double-buffering, support for continuous processing of data, the overall structure shown in Figure 1.


Figure 1, the overall structure of the decoder

H due to the support of three different array LDPC codes, so the port needs to have a model to inform the decoder which are the current data block pattern. Register controls the input mode selector to choose a different H matrix addressing module configuration control and to enable them to select the node to update the checksum of RAM and need to update the node unit (CNU), the variable node unit (VNU) circuit Buildings.

Input data input to input buffer RAM first group, the input buffer RAM set number of columns in accordance with the basic matrix is ??divided into N blocks of data cache, which can be configured N, N used in the text is 72. A coded data block is full, you enter into the node RAM group. RAM is the role of the node group iterative algorithm updates the information stored in the middle. Because there are more fundamental matrix zero matrix, so the actual number of generated nodes in RAM is much less than M N one.

CNU is the use of the circuit to do the probability of check node update, perfect (3) calculations. The structures shown in Figure 2 (a) below. VNU is the use of the circuit to do the probability of the variable node updates, hard decision also calculated the results, perfect (4) and (5) calculation.

Concrete structure shown in Figure 2 (b) below.


Figure 2 CNU and VNU circuit structure

Output cache RAM group was used to store and output decoding results, also taken a ping-pong operation, support continuous input and output data blocks. Control and address decoder module is the core module, which provides for the decoding control signals and addressing signals to read and write RAM. Addressing module is divided into CNU and VNU address generation module address generation module in two parts, CNU address generation module start address is the offset value; and VNU address is the address generated is from 0 to Z.

As a result of input and output double buffer, so the decoder can exist up to three data blocks, while blocks of data that can be three different pieces of data rate, which implements the different rate of continuous input Adaptive data block decoding function.

4 FPGA implementation and performance testing:

Based on the above design, selection of Verilog HDL design, while using Modelsim 6.1b to the simulation results, and finally STratix IIEP2S180F1020I4 chips were tested. Detailed in Table 1 below. Table 1 Resources

occupancy


Also listed in Table 1, a single-rate decoder resources (7 / 8 rate.) It can be seen in the multi-rate decoder is not more than two kinds of resource consumption rate and the decoder resources can effectively support the premise 3 rate.

Also were tested for each of its throughput rate and the maximum operating clock rate of which three (1 / 2, 3 / 4, 7 / 8), maximum clock work are 110 MHz, the highest throughput was 110 Mb / s, 165 Mb / s and 192.5 Mb / s. It can be seen from the test results, the throughput of multi-rate decoder are 110 Mb / s or more, indicating that meet the needs of adaptive multi-rate applications, while still maintaining a high decoding throughput.

5 Conclusion

For QC-LDPC codes, we proposed a multi-rate QC-LDPC decoder implementations, and with the FPGA implementation of this multi-rate universal decoder, supports at least three different types of QC codes -LDPC codes. This multi-rate QC-LDPC decoder can input and output parameters required to support flexible configuration of the pattern, and ultimately the decoding throughput rate can be any Chao Guo 110 Mb / s, taking into account the multi-rate translation encoder the flexibility and high throughput.

PI5C3257QX datasheetPI5C3257QX suppliersPI5C3257QX Price

All right reserved:icfull.com © 2010-2016 Certificate