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IEEE1394 bus, high-speed network communication system

In Electronic Infomation Category: I | on April 20,2011

Abstract: The high-speed network communication system network construction, topology, node structure, a detailed description of the overall system design, hardware design, software design and EPF10K50VBC356-4 datasheet and working process. The experiments show that the network can achieve maximum 400 Mb / s high-speed data transmission in real time, proved that the network communication system is feasible and EPF10K50VBC356-4 price and high reliability.


IEEE1394 serial bus as a high-performance technology with high data transfer rate, supports asynchronous and EPF10K50VBC356-4 suppliers and isochronous transfers, point to point connection, hot-swappable, cable provides power, etc. [1]. Multiple devices can be daisy * tree or chain topology to connect to the network, and share the bus bandwidth. Although IEEE1394a protocol is relatively complex, but low power consumption, data transmission is more stable, Zu Wangfang it (no router) [2]. IEEE1394 high-speed communication has demonstrated excellent performance of data transmission and ensure data security and reliability.

1 system program

IEEE1394 high-speed network communication system to build a tree topology network, the host computer through the software set on the root node 1394, node 1394, on the other device is set to a leaf node is intended to enable the host computer to on the control and supervision of the entire network. Build a good network topology shown in Figure 1.

Figure 1 high-speed network communication system topology diagram

In Figure 1, root and leaf nodes, leaf nodes and leaf nodes are used IEEE1394a standard cable connection. Under the root node of the network in two trees, theyre all on the same bus Bus0. 1394 is not a tree node can be in the same device, such as Node1, Node2 and Node5 all in one device.

2 Hardware Design

1394 nodes on the host computer uses PowerPC as the communication and data processing core. The reason is that it uses PowerPC architecture is open, but in large amounts of data PowerPC, high-speed signal processing has a strong advantage and a good application potential. Since most have a PC, PCI Interface, PCI bus is widely used, PCI interface driver of the GM is strong, so the host computer and the PowerPC host computer through the PCI interface to communicate, which simplifies the host computer on the PCI interface driver development work. The IEEE 1394 interface, a dual interface chip design, and equipped with SDRAM as a large capacity data buffer, using Flash to store the software. 1394 nodes are connected through the 1394 bus. 1394 on the host computer node (set to root) through the 1394 bus and a device on the network in 1394 of other nodes (leaf nodes have been set) connected to the overall block diagram shown in Figure 2. Root structure of the left, the right structure for the leaf nodes. Leaf nodes of the structure and root structure is similar, but only the root node and the host computer is connected, and the leaf nodes are not connected with the host computer, so the leaf nodes do not need PCI bus.

Figure 2 node 1394 on the host computer architecture

IEEE1394 interface, the chip uses a link layer and physical layer chip TSB12LV32 TSB41AB3. TSB41AB3 3 cable interface to support the physical layer chip. TSB12LV32 supports IEEE1394a bus standard is a generic link layer of high-performance chips, the maximum transfer rate of 400 Mb / s [5], the network can adopt 100 Mb / s, 200 Mb / s, 400 Mb / s for data transmission. TSB12LV32 provided for the back-end host interface, the system uses the host interface in PowerPC complete the configuration registers and asynchronous stream packet transmission. TSB12LV32 also provides a PowerPC and programmable interrupt output INT state STAT [0:2], for the bus reset, transmission errors and internal FIFO status indication.

To send and receive data, using DMA for data handling and completion. Through the interrupt mechanism to report the incident to receive the message to the core processor, PowerPC, the message for processing by the processor.

Figure 3 software hierarchical graph

3 Software Design

According to the software functionality to be achieved, the software can be divided into three levels, shown in Figure 3.

3.1 1394 core software

On the 1394 kernel registers the physical layer and link layer configuration, for OHCI, the bus manager configuration [3], and these core functions of the package. This isolation has the advantage of users do not make the underlying hardware, simply call the kernel function can be developed user software. Through the establishment of structures to classify these functions, link, driver software called the kernel function directly through the structure to find the appropriate kernel function, which calls, so put the 1394 kernel driver software and the link up top.

3.2 driver software

The 1394 protocol supports asynchronous transmission and isochronous transmission, and in order to ensure transmission reliability, so the use of asynchronous stream packet data transmission. For the transmission, the driver software first asynchronous stream packet according to the format of the messages on the communication software package for framing, and then send the call to the kernel function. For the reception, is to use the interrupt mechanism to receive messages.

3.3 communications software

Power, the 1394 will first appear on the bus about 125 s continuously reset the bus (bus reset) state, after the tree identification and self-identification work. Tree identification process in the definition of a bus topology. Before the tree logo, each node knows 1394 and the other nodes, after this process, the entire network topology to form, and set the computer to the root node (root), the other nodes for the branch nodes. After the tree identification process is a self-identity, self-identifying identification authorized by the signal sent from the root node and node self-ID packet to return to complete the function of its implementation are: the physical ID assigned to each node, neighboring nodes exchange information transmission speed , the tree identification process in the entire network topology definition broadcast.

The kernel function to initialize the entire communication network, including the PCI bus initialization init_pci (), initialize the 1394 device init_1394dev (), tree identification and self-identity, the host computer is set on the root node 1394 node (leaf node does not make this step), the initialization interruption.

After initialization, the first hook interrupt service routine. Then the root node by sending STOF package for network synchronization, that is to send STOF package as a start, the leaf nodes immediately after receiving STOF packets across the network synchronization. For the sending process, communications software to send the message to be passed to the driver software for transmission. For the receiving process, if the new message is received, will be reported to the interrupt to the processor, and according to the interrupt number into the appropriate interrupt service routine, interrupt service routine will set the flag bit to inform the receiver functions in the communications software to receive messages for processing.


Communication system with high-speed network communication requirements, to design the network communication system to complete the network between the host computer and the network, root and leaf nodes, leaf nodes and the communication between leaf nodes, experiments show that , the system communication is good. Because of this network follows the IEEE1394 standard, can be applied to digital home network, telematics systems, industrial automation systems, etc. [4]. With the continuous development of IEEE1394 technology, its application to more areas from business expansion.

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