In Electronic Infomation Category: H | on April 19,2011

Abstract: From the ADC input signal and **MAX4426ESA datasheet** and clock source set their own parameters, the main analysis of the input signal amplitude, frequency, sampling frequency of ADC clock jitter and **MAX4426ESA price** and signal to noise ratio, manual data according to information provided by ADC is given the calculation of the clock jitter, and **MAX4426ESA suppliers** and the calculation results and the actual measurement results were analyzed and compared, and further proposed to reduce the clock jitter method.

With the rapid development of information industry, on the A / D, D / A increasingly high performance requirements. Currently, for high-speed, high-precision ADC is active in research. ADC sampling clock is to transform the basic elements of the circuit, in terms of circuit designers, ADC clock program clock circuit, clock type, clock voltage levels, clock jitter is in the actual circuit design must be taken into account. Sampling clock jitter is a short-term, non-cumulative variables, that the real time digital signal and its ideal position location time deviation. ADC clock jitter will trigger an internal circuit error sampling time, resulting in the analog input signal amplitude of the error in the sampling, which worsened the ADCs SNR, the sampling clock jitter on high-speed, high-precision ADC performance can not be ignored .

Figure 1 shows a typical ADC clock circuit, high-speed ADC, such as ADS5500, often using this clock structure. In this paper, the clock circuit shown in Figure 1, the parameters of the internal clock on the ADC performance, the results for the design of the external clock circuit reference.

Figure 1 A typical ADC clock circuit

** 1 jitter and Ain, fin, fS relationship **

** Start sampling clock signal is sampled to maintain control until the internal sample and hold circuit switch is closed, the capacitor voltage track the analog input signal changes, the arrival of the clock signal when an edge switch, the capacitor voltage to maintain the value of the moment . Shown in Figure 2, the moment the voltage value corresponding to the value of the vertical dotted lines in the sampling time t, the voltage produced a sampling error of V, the instantaneous error is clock jitter Jitter, sample size depends on the voltage error the input voltage waveform. If no other noise signals, according to Figure 2, the voltage can be calculated the size of jitter and SNR. If Figure 1 for the amplitude of the input signal Ain, fin frequency sine wave, the sampling clock jitter Jitter voltage proportional to the input voltage at the time of the slope and sampling time. Then a cycle of the square of RMS clock jitter Jitter 2 is: **

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** Full Text PDF Download: high-speed ADC clock jitter and Its Influence. Pdf **

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