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FPGA-based video format conversion system

In Electronic Infomation Category: F | on April 14,2011

Abstract: According to TV standard PAL / NTSC signal output VGA display format of the solution in detail about the video format conversion system based on FPGA Design and DAC2814AP datasheet and Implementation. By Cyclone series EP3C1 * 84C6 as the core processing devices, to achieve the NTSC / PAL standard video decoding, color space conversion (CSC), frame rate conversion and DAC2814AP price and interlaced progressive conversion, scaling, video DAC conversion, and DAC2814AP suppliers and ultimately the component R, G, B of the VGA video output video format, resolution up to 1 600 1 200 @ 100 Hz.

1 System Design

Design uses the EP3C1 * 84C6 models ALTERA FPGA as the core video processing, connecting two pieces of DDR2 SDRAM, DDR2 chip model M icron the MT47H 32M16BN _37E, as the systems data storage device, a bandwidth of 32 bit, the clock rate 200MHz, the data rate of 400 Mbps. Video decoder chip for the TVP5147, Video DAC with high-performance ADV7123. The framework of the system shown in Figure 1.

video processing board block diagram of Figure 1

2 hardware module.

2. 1 video decoder

TVP5147 the decoding process shown in Figure 2.

Figure 2 TVP5147 decoding process

TVP5147 video decoder chip reset, the MCU to its correctly configured through the I2C registers. This article TVP5147 I2C-register configuration of the value shown in Table 1.

Table 1 TVP5147 I2C-register settings

2. 2 video memory

In the video processing module includes a large number of video data memory module, can be divided into the line memory, frame memory and look-up table memory in Class 3.

(1) line of memory for storing video data in a row, due to small data achieved with the FPGA internal RAM.

(2) a frame memory for storing video data, due to large amount of data, with the DDR2 to achieve.

(3) look-up table memory for the corresponding input and output resulting in irregular, such as Sin function and Gamma correction curve.

2. 3 FPGA module design

FPGA module design shown in Figure 3.

Figure 3 FPGA block diagram

2. 3. 1 data string, and conversion and chroma re-sampling module

This module is divided into series and conversion and chroma resampling two parts.

String and convert the output mainly to the TVP5147 component of the mixed data into the data. As a result of BT. 656 10 - b it 4:2:2 mode, the output data clock for the pixel clock (13. 5 MHz) twice, the output data were Cb0, Y0, C r0, Y1, Cb1, Y2 , C r1, etc., this module will be converted to 4:2:2 YCbCr its component data, RTL simulation results shown in Figure 4.

Figure 4 string and conversion module simulation results Although the video component

bring a better image transmission reduction degree, it also brings increased data bandwidth, so many times people are not so important to the visual color difference signals were re-sampled to 4: 2:2 (or 4:1:1) to reduce the transmission of data bandwidth. Video and display systems in use within the basic 4:4:4 signal, so chroma resampling video conversion has become an essential module. This implements the 4:2:2 to 4% 4% 4 and 4:4:4 to 4:2:2 conversion. 4:2:2 to 4:4:4 conversion method has a direct repetition, one-dimensional filtering and brightness adaptive filtering method.

Consider the hardware cost and processing quality, we use one-dimensional filter, which only consider the color filter channels in the horizontal direction. Figure 5 is carried out using n-tap FIR filter block diagram chroma resampling.

4:2:2 to 4:4:4 chroma Figure 5 re-sampling module

2. 3. 2 color space conversion module (CSC)

Due to different video standards use different color space, and some video processing needs to deal with a specific color space, color space conversion is therefore essential. Color space conversion is actually a three-input obtained by linear matrix transformation of the three new output, the basic conversion formula is as follows:

On the type of Ax, Bx, Cx, Sx represent the conversion factor between the different spaces. General video systems, including color space involved in the computer R G B space, NTSC and PALs YUV space, and YCbCr space. Figure 6 block diagram for the conversion, the conversion factor which can be any configuration, that standard does not qualify. On the section 10 b it YCrCb can use this color space converter, with the SD to HD conversion factor into 8 b its BT. 709 Standard YCrC data.

Figure 6, color space conversion module (Rx for the round ing value)

Input 8 bit of RG B signal, first by R G B to YCbC r 10 b it into the Y CbC r signal, and then transfer into the 8 bit of R G B signal. Color space conversion which is used in high-definition standards, using the fractional part of the 16 b it to handle fixed-point decimal conversion factor. Figure 8 bit upper part of the RGB data input, the middle 10 b its YCrCb data, the next part 8 b its RGB data output. Because the pipeline deal done, the output has 3 clock delay.

Figure 7 8 b its RGB switch to 10 bits Y CbC r and then back to 8 b its RGB simulation results

2. 3. 3 frame rate conversion and interlace progressive conversion module Progressive interlaced method

turn can be divided into spatial and temporal aspects. Airspace algorithm is simple and easily implemented in hardware, the common line and a direct repeat interpolation in the vertical direction the rows are missing. Time-domain method involves computation between adjacent fields, common methods of blending the fields, motion-adaptive de-interlacing algorithms and complexity, the highest de-interlacing algorithm for motion compensation. This trade-off method using the hybrid market, is about to field data synthesis between two adjacent fields to progressive frames of data, shown in Figure 8.

Figure 8 shows mixed interlaced progressive realization of transformation

PAL and SECAM formats of the field frequency is 50 Hz, and NTSC for the 60H z, when the need for different field frequency signal superimposed on the need for field frequency conversion. Most video equipment used in frame rate 60 H z, so this involves only 50 ~ 60 H z the frame rate conversion. Commonly used methods are field duplicate, field interpolation, motion compensation method, in which field interpolation algorithm shown in Figure 9.

Figure 9 50 Hz 60 Hz field transfer interpolation method

For the PAL format from the above figure shows the two, as long as both read 3-line interlaced field data that can achieve a progressive transformation and frame rate conversion to complete. Frame 1 as the output from the input field data to determine 1,2, and the output of the first two games by the input data to determine the first 1,2,3, and output section 3 by the input section 2,3, 4 field data to determine, and so on.

System uses 48-bit wide DDR2 memory as for the field of memory DDR2 controller in the FPGA side data inside width of 96. Frame 2 as the output generated process is, when deposited in a field, block out the high 64bit do not write, write the low-field data 32 b it (actually only using 30 b it). Deposited in Game 2 when the high 32 and low 32 b it is not masked write, and write 32 bit field in the middle of the data. When deposited in Game 3, to block out the low 64 b it does not write, and write 32 bit high-field data. So that data can be read when the order of 3 field data simultaneously read out, then the combination of the above interpolation, the output can be obtained. Field within the format of the data memory shown in Figure 10.

Figure 10 can be achieved at the same time de-interlacing and frame rate conversion of the field memory

Attention to the new input field data can not overwrite adjacent data, so when the mask bit stored in the data is constantly beating, and for a period of 5 games. Although this reduces the efficiency of writing, but because of all the data read and write operations are sequential, so a whole is still access to improved efficiency of DDR2, and make the operation easier. For NTSC, the frame rate conversion component can not be considered, you can only use part of low-two 64-bit storage.

2. 3. 4 zoom module

Video scaling, including zoom (up scaling) and narrow (downsca ling) two aspects, while the basic method of scaling the spatial interpolation. The following formula for the interpolation of the image general mathematical expression, in which g (i, j) to zoom the image pixel value interpolation points, f (k, l) for the original image coordinates (k, l) at the pixel value, h (i-k, j - l) for the interpolation basis function.

Interpolation basis function can have a variety of options, usually two-dimensional rectangular function, linear function, cubic function, and S inc function, and these correspond to the nearest neighbor interpolation, linear interpolation, cubic interpolation and the ideal interpolation (the actual use of truncated interpolation function S inc), the interpolation results from poor to good order, but also in turn increase the difficulty to achieve. In the actual processing is the use of filters to achieve the interpolation basis function, and because of the symmetry of the interpolation can be decomposed into horizontal and vertical interpolation of two parts separately, such as two-dimensional linear interpolation function corresponding to bilinear interpolation (Bilinear Interpo lation), three times the corresponding bicubic interpolation function (B icub ic Interpo lation), Sinc interpolation function for the actual interpolation for multi-phase (Po lyphase Interpo lation). This article uses the multi-phase interpolation of image scaling, in fact, in 4? 4 size within the field of multi-phase interpolation and cubic interpolation is almost the same, but slightly different values ??of the corresponding interpolation functions. Multi-phase interpolation point corresponding to the output through the original function in the areas of Lanczos2 phase interpolation to generate the output point. Shown in Figure 11.

Figure 11 Lanczos2 function

Assume g (u, v) is by scaling the output image after the point, its reduction to the nearest point of the original image f (i, j) and the difference between the original (x, y) coordinates, then Output g (u, v) the following mathematical expression, its effect can be seen separately in two steps to achieve the level of vertical filtering and filtering.

Including relationship: i = (u W in) / W out, j = (v H in) / H out; x = (u W in)% W out, y = (v H in)% H out. W in and Wout, respectively before and after scaling the image width, H in and H out before and after images were scaled height. Figure 12 is 4 4 field of horizontal and vertical phase, in which the level of the phase values ??were PH 0, PH 1, PH 2, PH 3, the vertical phase values ??were PV0, PV1, PV2, PV3. Obtained under the above relationship as long as x, y value of the phase values ??can get 8, you can multi-phase filtering.

Figure 12 4 4 field of horizontal and vertical phase

Figure 13 is an image scaler designed in this paper in the filter part of the diagram, in which the vertical and horizontal lookup table stored separately with four different phases Lanczos2 function value.

in Figure 13, the image scaler filter

2. 4 Video DAC

Video coding to the analog R, G, B by the video DAC chip ADV7123, it has three independent channels within the 10 bit high speed DAC, as shown in Figure 14, the role of its functional diagram of the system.

Figure 14 ADV7123 system diagram

3 system power supply design

Power supply reliability is the key to the success of electronic system design. In the design of power, in ensuring the reliability of the power necessary to consider the basis of efficiency and volume of power supply circuit, the system needs to 0. 9 V, 1. 2 V, 1. 8 V, 2. 5 V, 3. 3 V, 5 V power supply a total of 6.

LM2737 output current up to 5 A, efficiency 90%, package SO IC, small size. The VTT and DDR2 VRef of 0. 9 V voltage reference by the DDR termination voltage converted from general-purpose chip TPS51100.

block diagram of Figure 15 Power Supply

4 Conclusion

This paper, C yc lone III of EP3C1 * 84C6 devices and related video codec chip design video format conversion system to realize the ordinary television signal to a more generic VGA interface signal conversion, through the scaling of the video signal treatment increases the video resolution. In addition, the use of FPGA as the core video processing devices, making the system support the video format has good flexibility.

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