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FPGA-based two-way IEEE-1394b data transmission system

In Electronic Infomation Category: F | on April 14,2011

With the IEEE Std 1394-1995

the rapid development of technology, IEEE 1394 has become a large electronic equipment basic external interfaces. However, to further expand its field of application, it must overcome its interface is limited to work in a shorter distance and XC79185FN datasheet and higher data rate does not apply to defects. IEEE Std 1394b-2002 amendment version of its support for 800 Mb s-1 transmission rate, and XC79185FN price and the relay distances of up to 100m. It will be the original DS (Data-Strobe) improved to 8B/10B encoding encoding, this performance improvement for 1394 played a decisive role. At the same time, 1394b is backward compatible, meaning that the same can choose to use either a circuit can also choose to use the DS 8B/10B encoding encoding. Now meet the standards

1394b link layer and XC79185FN suppliers and physical layer controller chip will follow the 1394 OHCI (Open Host Controller Interface Protocol), its main function is to implement the bus of the link layer protocol. NIOSII processor through the system, according to 1394 OHCI, and the 1394 chip set on the FPGA to control, to achieve a two-way data transmission. Its main function is to an external video data package, in accordance with the 1394b protocol, real-time transmission to the host-side display, and to achieve mutual communication with the host.

1 1394 OHCI features

Support transaction and bus management layer, but with a PCI host bus interface, and high-speed data transfer DMA engine needs. Supports two data transfer: asynchronous transfer and isochronous transfer.

Asynchronous Transfer: 1394 OHCI can send and receive all defined 1394 packet formats. Whether it is read from the host memory to send data packets, or the received packet writing host memory through DMA to achieve. Storage space to the host bus read and write when, 1394 OHCI can also read and write requests directly to the implementation of the 1394 and 1394 as the host bus bridge between the bus.

Isochronous transfers: 1394 OHCI controller can perform the function of circulation. That it contains a cycle timer and counter, 8 kHz clock can be arranged after each rising edge of a cycle start packet transmission. 1394 OHCI can generate an internal clock. Loop controller when it is not, 1394 OHCI cycle started under the package, by correcting the cycle timer to maintain its internal clock synchronized with the master node of the cycle. 1394 OHCI such as such as when sending and receiving time of each provides a DMA controller. Each DMA controller supports up to 32 different DMA context (context). Such as DMA controller can be sent in each cycle to send data from each context. And each context can only be when the only other channel to send data. Isochronous Receive DMA controller in each cycle to receive data from each context. However, both the context of each other from the time the only channel to receive data, such as the time from multiple channels to receive data.

2 hardware NIOSII

to FPGA embedded processor development platform, control two-way data transmission. The hardware block diagram shown in Figure 1. Mainly by the system module NIOSII, SPI port data input and output module, 1394 chip set module, SRAM modules, the serial port (UART) communication module, power management module, EPCS modules and Flash module. Which, FPGA chip as the main control chip, the company selected Ahera Cyclone II family EP2C70F672C8N; Flash chips used to store NIOSII code and data embedded processors, FPGA after power from which to read; SRAM chip, one for a lot of video on the external data cache, and the other as the C code to run space. Mainly used to generate the serial asynchronous data, the external video data is carried out mainly through the SPI port isochronous transfer.


Figure 1 System hardware block diagram

3 software workflow

In NIOSII IDE integrated environment, in accordance with 1394 OHCI agreement, so that the bus NIOSII processor initialization, and management, and be achieved through the DMA isochronous and asynchronous data transmission. Isochronous data transmission in which only consider the external video data package sent to the host, and asynchronous data transfer initiated into the host device initiates the asynchronous transmission and asynchronous transmission 1394.

3.1 system bootstrap

Mainly for system initialization and testing cables and the determination of the root node. System initialization key is to configure the link layer chip registers, needed to work in the state. Into registers of the PCI registers initialization and the initialization of the OHCI. Register on the PCI device initialization including TSB82AA2 PCI vendor ID and ID verification, OHCI base address register set and the configuration status register directives. The initialization of the OHCI registers include registers for each interrupt and DMA context settings, and control register configuration. Detection of the cable is plugged into a physical layer chip by reading the corresponding bit in a register, to judge. Cable is inserted through the inspection and configuration of Node ID register, forces the child node of this node, the host for the root node, until it succeeds.

3.2 data transmission

In 1394 OHCI, whether it is isochronous transfer or asynchronous transfer mode is achieved through the DMA, and each has a DMA FIFO, used to temporarily store data. In which the storage capacity of the FIFO: asynchronous transmission (AT) FIFO is 5 kB, asynchronous receiver (AR) F7FO to 2 kB, etc. send (IT) fIFO to 2 kB, such as when the receiver (IR) FIFO is 2 kB. Whether or physical layer receives data packets to be sent out, are temporarily stored in the corresponding FIFO in the 1394 chip set by the internal logic of control will send it to the 1394 bus.

(1) host-initiated asynchronous transmission.

Host that initiated the asynchronous transmission asynchronous transfer request issued by the host, the 1394 device to respond, so this part is mainly asynchronous request to receive the package and send an asynchronous response packet. The workflow shown in Figure 2. 1394 to the host device receives the asynchronous request packet sent after receiving the request will generate an asynchronous interrupt, which by the link layer chip interrupt register RQPkt bit representation. When a packet transmission is completed, the last instruction packet descriptor xferStatus field will be reset when a packet has been successfully transferred to the AT response FIFO.


Figure 2 Host-initiated asynchronous transfer processes

(2) 1394 device initiates the asynchronous transmission.

Similarly, initiated by the 1394 device is asynchronous transfer equipment from the 1394 issue of asynchronous transfer request, the host response. Therefore, this component is to send an asynchronous request packet and the asynchronous response packet received, the workflow shown in Figure 3. Then generates an asynchronous DMA interrupt request output, which can break the link layer chip registers reqTxComplete bit representation. 1394 sent to the host device receives the asynchronous response packet, it will generate an asynchronous interrupt to receive a response, which can break through the link layer chip registers that. In addition, the request packet sent will also be temporarily stored in memory in order to correspond with the return of the response packet.


1394 device in Figure 3 Asynchronous Transfer initiated the workflow

(3) when such transfer.

Isochronous transfer function is achieved mainly through the 1394 device when the external video data, real-time transmission to the host display. External video data associated with the FPGAs SPI interfaces, FPGA to receive the data cached in the SRAM, so when the transmission, FPGA reads the data in the SRAM to generate isochronous packets. This part of the main job is to send the isochronous packet, and its work flow shown in Figure 4.


Figure 4 isochronous transfer workflow

4 test results of

Order to test the system performance, for the fastest transfer speed tests. Set the bus transfer speed of 800Mb s-1, according to the provisions of the 1394 bus protocol, each packet a maximum of 4 096 bit. A transmission cycle of 125s theoretically send a packet, so transmission of data per second, up to 31.25 Mb, converted to a bit rate, maximum transmission speed of 250 Mb s-1. Measured up to the fastest transmission speed of 227 Mb s-1, compared to 1394a theoretical maximum speed of 125 Mb s-1 increased more, so the transmission speed of the system has a greater advantage. Meanwhile, the host-side real-time display of video in real time and reliability are better.

5 Conclusion

The system, using 800 Mb s-1 of the bus transfer rate, the use of FPGA embedded NIOSII processor was used to achieve a two-way transmission, asynchronous transfer mode transmission with the host-side instruction and camera position and status information with other means of transmission when the camera is transmitted to the host-side data in real time display. Experiments show that, compared to 1394a, the program has high-speed communications, high reliability, real-time and other advantages, to achieve the intended goal, running well. The 1394 system is communication between devices and hosts, on this basis can also study from the computers environment, communication between two devices transmit 1394 and the transmission network of multiple devices.

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