In Electronic Infomation Category: F | on April 22,2011

Abstract: The first analysis of the soft 8PSK demodulation principle, for the best log-likelihood ratio (LLR) the characteristics of high computational complexity, the choice of a relatively simplified maximum (MAX) algorithm as a programmable logic gate array (FGPA) hardware platform implementations. Subsequently, by QUARTUS II simulation platform for 8PSK demodulator soft hardware description language (VHDL) design and **AD8349AREZ datasheet** and implementation, and **AD8349AREZ price** and functional simulation, and **AD8349AREZ suppliers** and with the LDPC decoding module cascade in Alteras FPGA chip STratix II series of final test . By comparison with the MATLAB simulation results to verify the simplified soft 8PSK demodulator design is correct and feasible.

** 0 Introduction With satellite communications services **

** development, people have become increasingly demanding quality of service. In 2003, the satellite digital video broadcasting (DVB-S2) system uses an efficient low density parity check (LDPC), increased by about 30% of the bandwidth efficiency. Well known, commonly used in satellite communication system with BCH concatenated LDPC forward error correction coding to achieve high performance requirements in order to achieve this performance, the received signal in the demodulation part of the need to use soft demodulation, and therefore higher order modulation system (eg, 8PSK), the need for an appropriate, simple and easy to realize the soft modem technology to map the received signal solutions. In traditional wireless communication system design, log likelihood ratio (LLR) algorithm for optimal algorithm performance is often used as a soft decision technique, however, because the algorithm complexity is too high, involving several of the number and index operations, not suitable for hardware implementation, so a lot of Soft Decision algorithm simplification has emerged. Where the maximum (MAX) algorithm based on the LLR algorithm simplifies the index and the number of operations, the hardware implementation complexity significantly reduced compared with the LLR, while small compared to loss of LLR algorithm performance. Therefore, in the communication system hardware design, usually used as a MAX algorithm soft demodulation algorithm suitable for soft demodulation of the received signal. This first analysis of the 8PSK **

** soft demodulation algorithm complexity and the basic principles of MAX algorithm, and Alteras Stratix II family FPGA chip to achieve this soft demodulation hardware module, the module also carried out with the LDPC decoding Joint verification. Through software and hardware verification and analysis show that the design of computational complexity, throughput, BER performance eventually made good compromise. **

** 1 8PSK demodulation software **

** 8PSK modulation constellation shown in Figure 1, each symbol represents three bits, equation (1) that after a Gaussian white noise channel the received signal after the probability density function, equation (2) describes the constellation map The value of each constellation point, Si represents the constellation constellation on the 1-8 point. **

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** Figure 1 8PSK modulation constellation **

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** Where is the Gaussian white noise channel standard deviation. By LLR algorithm, soft decision as equation (3) shows, which means that the molecules of the probability of bit 0 and the denominator indicates that this bit is 1 the probability of and. **

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** From (2) and (3) can be seen, each computing one bit of LLR, need to square, exponential and logarithmic operations, the LLR algorithm has higher computational complexity and greater resource overhead particular hardware implementation index, the number of high complexity, so the LLR algorithm is not suitable for FPGA implementation. The maximum (MAX) algorithm can effectively avoid the calculation of the log-likelihood of each bit value of the index and the number of operations, the principle of such type (4). **

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** By (3) and (4) indicates that after the MAX algorithm is as follows simplified formula (5) shows, for the type (3) and (5) we can see, LLR algorithm in hardware is difficult to achieve index logarithmic, and MAX algorithm only requires a few simple addition and subtraction and multiplication, easy hardware implementation project, so select the MAX algorithm as a hardware implementation of the final plan. **

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** 2 Performance Analysis **

** By MATLAB simulation platform, made the following comparative analysis of performance simulation. **

** Generated by the MATLAB random sequence of a length of 100 000 coding blocks, each encoded block to 4 032 bit, then through rate is 1 / 2 LDPC coding module, through the corresponding 8PSK modulation, the Eb / N0 is 4 dB to 7 dB in the range, respectively, after LLR optimal algorithm, floating-point MAX algorithm, fixed-point algorithm is calculated MAX log-likelihood ratio, respectively, after LDPC decoding module finally obtained BER performance. **

** Table 1 is calculated by MATLAB simulation platform corresponding to each Eb/N0 error rate, Figure 2 is the corresponding BER curves. Figure 2 shows, the test interval for Eb/N0 4 dB to 7 dB in any one test point, LLR bit error rate better than the best fixed-point algorithm MAX MAX algorithm and floating-point algorithms to be small, in which floating-point error MAX algorithm code performance center, point-MAX algorithm is the worst. MAX algorithm performance by reducing error in exchange for reduced computational complexity, the BER performance worse than the optimal algorithm of LLR. MAX with the floating-point algorithm, fixed-point algorithm for MAX soft demodulation module input I, Q signals and outputs two likelihood ratio cut-off position were carried out and limiting, as shown in Figure 2, relative to fixed-point algorithm for MAX MAX algorithm floating a certain error performance loss. We can see from the table, point-MAX algorithm is 6.64 dB Eb/N0, its bit error rate of 6.5125 10-8, verify that the fixed-point program to meet system design requirements. **

** Table 1 MATLAB BER simulation table **

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** Figure 2 MATLAB BER simulation **

** 3 MAX algorithm for hardware implementation **

** The hardware is fixed-point arithmetic, so the MAX algorithm implementation is the MAX fixed-point algorithm for hardware design. Hardware simulation flow diagram shown in Figure 3, the first use MATLAB to generate random sequences, assuming that each encoded block 4032 bit, LDPC coding efficiency of 1 / 2 rate, the LDPC encoded by each block is 8 064 bit encoding , the 8PSK modulated symbols, each block is an encoded modulation symbols into 2688, real part imaginary part of the I, Q two, and then superimposed noise ratio SNR of the Gaussian white noise, and finally the data files are stored in RAM. In the hardware implementation, the soft demodulator module MAX point to a certain rate of reading data from RAM and the soft demodulation and soft demodulation output of the log-likelihood ratio is stored in the ping-pong RAM, each one is full to the LDPC block codes decoder sends a read valid signal, LDPC decoder receives the valid signal in the next clock cycle, a certain rate began to read the entire code block on the log-likelihood value, and then start LDPC decoding, and finally be the final decoding result output rate. **

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** Figure 3, the hardware design and simulation **

** 4 Hardware Design Analysis **

** Verify the performance of a soft demodulation module is good or bad, you need to simulate the cascade decoding module integrated authentication. In the hardware design, by higher Stratix II FPGA hardware platform module associated with the MAX fixed-point algorithm for LDPC decoding algorithm module, and then integrated wiring, and finally downloaded to the hardware platform for testing. **

** The simulation used by the project file to add observation Chipscope sampling signal, trigger signal and the signal to be seen again after synthesis, placement and routing generate bit file after downloading to the target board with Chipscope online testing, and input by the output bits flow compared to verify the design correctness. Comprehensive report of QUARTUS II, addition and subtraction only instruments used in the design module, part of the register and 16 multiplication modules, the use of fewer resources to meet the low complexity, high-throughput design requirements. **

** 5 Conclusion **

** The LLR algorithm has higher computational complexity, the hardware is not easy to achieve, and the MAX algorithm is simplified to avoid the index and the number of operations, significantly reduce the computational complexity, only a small number of the addition and subtraction and multiplication, suitable for hardware implementation. The design is controlled by MATLAB and the VHDL simulation to verify the hardware design MAX soft demodulation algorithm accuracy, both the module and the LDPC decoding module cascade, in the specific FPGA chip to run, using on-chip to further validate the design analyzer Chipscope feasibility. **

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