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FPGA-based intelligent instrument remote control system

In Electronic Infomation Category: F | on April 20,2011

Abstract: intelligent instruments for the remote control and AD73311LARSZ datasheet and improve the speed control system using field programmable gate array (FPGA) chip, USB chips to achieve the intelligent instrument remote control system. Focuses on the interface RS 232 and AD73311LARSZ price and USB conversion principle and AD73311LARSZ suppliers and FPGA programming and simulation. System uses a first in first out memory and finite state machine implementation of the RS 232 and USB interface conversion and host computer control, data processing and other functions. System can significantly reduce the workload of the host computer, not only for laboratory can also be used in industrial production.

Present intelligent instruments has been widely used in scientific research and industrial production were, but many machines scattered in different geographical location, easy to operate and maintain, and real-time tracking performance is poor, human error, the data can not be saved, while a large number of high-end instruments price is quite expensive. To solve the above problem, the computer prompts to complete the operation, can reduce the damage caused by human factors, and improve the accuracy of test data. As is the RS 232 interface, intelligent instruments, the PC using a USB interface, so the need to achieve by the FPGA and the USB interface between the RS232 conversion. The FPGA can run in parallel, high integration, available resources, and therefore use of FPGA for data processing, can reduce the workload of the host computer, reducing data processing time, you can shorten the design cycle, reducing board size, in order to facilitate integration to the other boards.

1 control system and interface profile

1. 1 system features

Throughout the system, host computer system to monitor real-time, and issued the appropriate command. Intelligent Instrument outgoing data sent through the RS 232 interfaces to the FPGA, FPGA based on PC commands issued decisions on these data, processing, and then through the USB interface to upload to the host computer, and then by the host computer processed data to the FPGA for display, storage and other operations.

1. 2 U SB interface chip Introduction This design uses the

CYPRESS Semiconductor EZUSBFX2 series chip CY7C68013. CY7C68013 is a high performance USB 2. 0 micro-controller, which provides comprehensive USB 2. 0 peripherals solutions. Mode with Port, Slave FIFO and GPIFMaster three, the program uses Slave FIFO mode. In this mode, the external controller (such as FPGA) may be the same as for ordinary FIFO on FX2 the end of 2, 4, 6, 8 of the data buffer read / write. 8051 FX2 firmware embedded function is related to the Slave FIFO configuration register, and control when working in FX2 Slave FIFO mode. Once the 8051 firmware, complete the relevant configuration register, and make their own work in the Slave FIFO mode, the external logic (eg FPGA) to the transmission timing according to Slave FIFO, high-speed communication with the host, but not in the communication process 8051 firmware participation.

1. 3 RS 232 Interface Overview

RS232C standard (protocol) is the full name EIARS232C standards. EIARS232C is used to indicate positive and negative voltage logic state, and T TL high-low logic state, said the requirements are different. Therefore, in order to work with a computer interface or TTL device connection terminals, must EIARS232C and T TL circuit level and the logical relationship between the transformation. Methods available to achieve this transformation of discrete components, integrated circuit chips can also be used. The design using a MAX3232 chip.

RS 232 data transmission format shown in Figure 1.

Figure 1 RS 232 standard data transmission format

RS 232 transmission format includes the start bit (1 b), valid data bits (8 b), parity bit (0 ~ 2 b), stop bit (1 b). Transmission line is high at idle, so the start bit is low, the stop bit is high.

Parity bit can be set to odd parity, even parity or no parity, data bits are valid starting from the low transmission.

2 FPGA design

2. 1 USB Interface Timing

In the Slav e FIFO mode, external logic signal with the FX2 connector shown in Figure 2.

Figure 2 FX2 Slave Mode Interface Pin Connection Diagram

In the Slav e FIFO mode, CY7C68013 chip port 2,4, 6, 8 to provide full-empty flag FLAGA, FLAGB, FLAGC, FLAGD. IFCLK output clock for the FX2 can be used for communications synchronization clock; SLCS for the FIFO chip-select signal; SLOE for the FIFO output enable; SLRD for the FIFO read signal; SLWR for the FIFO write signal. On the FPGA, the four ports were four FIFO.

FPGA testing four were full of empty flag to the corresponding FIFO read / write. FPGA can select synchronous or asynchronous read / write, in the design of the asynchronous read / write. Slave FIFO asynchronous write, the clock provided by the FPGA. Each data SLWR valid - invalid when the edges are written, FIFO write pointer increments. Asynchronous Slave FIFO Reading, FIFO read pointer in the SLRD each valid - invalid edges to change when the data increments.

2. 2 FPGA programming

FPGA design is the core of the system by the VHDL language. FPGA implementation of the USB and RS 232 interface, conversion, data processing, command transfer and other functions. With the above interface timing, they can FPGA design. FPGA part of the overall design shown in Figure 3. Modules:

USB and FPGA interface module: U SB and the interface between the FPGA conversion module, USB interface, the main function is to pass over the information is cached to the FPGA internal FIFO, and processed by the data processing module of the data to the U SB chip . Control signal that is read / write U SB chip FIFO. Can be read / write FIFO both finite state machine implementation.

To read the CY7C68013 chip data, for example, asynchronous read U SB according to the FIFO timing diagram can be divided into four states: idle state, choose the address state, ready to read the data state, read the data state, the state after reading [6]. In the idle state, when the reading time of the incident into the Select Address state; in the choice of the address state, so FIFOADR [1: 0] point to the OUT FIFO, ready to read data into the state; in preparing the data states, such as FIFO empty, waiting in this state Otherwise, read data into the state; in reading the data state, the SLOE, SLRD effective line readings from the data, then the SLRD invalid, the FIFO read pointer increments, and then make SLOE invalid, after reading into the state; in the state after reading, For more data transmission, ready to read data into the state, or enter the idle state.

Figure 3 FPGA block diagram of the overall design

USB data cache modules: distributed intelligent computer equipment used to cache instructions and other information. FPGA chip by the IP core generated first in first out memory FIFO. Capacity of 8 b * 512 depth. Takes a block RAM resources.

RS 232 data cache module: used to cache the data sent by the smart instrumentation. FPGA IP core generated by the first in first out memory FIFO. Capacity of 8 b * 512 depth, takes a block RAM resources.

RS 232 and the FPGA interface module: RS 232 interface between the conversion and the FPGA module. Main function is the string / and and and / serial conversion.

USB data cache module will be cached content to the appropriate rate of distributed intelligent devices through the serial port, and intelligent instruments issued to the RS 232 data cache data cache module. This module is realized by the two state machines. Have to set the baud rate serial communication, the baud rate used here is 9 600 Kb / s, using the clock to 50 MHz, the equivalent of sending a data need about 5028 clock cycles, where the counter to control the use of subtraction that the counter is to the 5028 clock cycles to begin transmitting the next data.

Data processing module: The main function of the host computer based on the instructions of the RS 232 data cache data to make appropriate treatment. Processing, then pass up the crew. The main treatment methods are regularly fetching, smoothing processing. Way to achieve implementation by the state machine. FPGA top-level modules: each module is mainly responsible for the flow of data flow between. And with external chip connected to the definition of input and output signals.

System at work, in the acquisition of PC data upload, the data channel is: intelligent instrument sends data through the RS 232 interface module RS232 data cache module exists in the cache. When the cache after a certain amount of data, and through the continuous data processing module to read the data in the FIFO and the host computer sends commands according to the corresponding data processing, and then will process the data with the FPGA through the USB interface, USB interface module to pass . In the control command issued by host computer, the data channel is: PC USB port to send commands to pass through the FPGA of the RS 232 interface module and the FPGA, this module is a data processing instruction to determine or control equipment instructions. If the data processing instruction, then let it pass to the data processing module to process data as required. If the command is to control the instrument, then the data cache module into the USB, then the RS 232 interface module and the FPGA to read, turn RS2322 format outgoing. The RS 232 interface, USB interface, faster than the slow, asynchronous with the internal FPGA clock rate matching FIFO to solve the problem.

Pass through the RS 232 over the data cache in the FIFO, and then to a certain amount of data stored and then removed all continuous, and so forth, in order to achieve continuous data acquisition and real-time PC display. Through the USB pass them on to another FIFO in the data cache, so that the rate of FPGA to read in accordance with RS232. This prevents USB RS 232 not keep pace with the speed and generated data loss.

3 simulation results

FPGA using the system clock frequency 50 MHz, simulation tools for the Mo delsim SE 6. 5a, a continuous simulation with the data 8 b data.

Simulation results shown in Figure 4.

Figure 4 FPGA USB internal FIFO simulation map reading

Figure 4 shows the FPGA FIFO read the simulation results of the internal USB, DATA for the analog data received from the USB port, the data already exists in the USB chip FIFO. FIFODAT A received data for the FPGA, can be seen from the previous, FPGA can be U SB out of the received data analysis.

Figure 5 for the RS 232 interfaces with the FPGA part of the simulation results. It can be seen from the RS 232 serial data RXD received have been converted to parallel data din. Program is a valid byte into the FIFO in it after the end, the figure can be verified. Figure 6 top-level block diagram simulation, in order to verify the data sent by the FPGA correctly received, first sent the data within the FPGA, and then the T XD RS 232 port issue, so that RXD and TXD connected to receive, we can see that given data can be correctly transmitted to the receiver back and U SB port, that the timing is correct. Similarly, you can verify U SB

end transceiver timing.

Figure 5 RS 232 receiver simulation diagram

Figure 6 top-level module simulation diagram

4 Concluding Remarks In this paper, FPGA implements

USB and RS 232 interfaces between the conversion and data processing functions. The design of first in first out memory used to solve the data cache and rate matching, the use of finite state machine design makes the program more clear and reliable. The design of complex signal operations will be concentrated in the FPGA to complete, the use of FPGAs unique parallel processing capabilities, while reducing the workload of the host computer to improve the system speed.

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