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FPGA-based high-performance DAC chip testing and research

In Electronic Infomation Category: F | on April 18,2011

D / A converter as digital and MAX1626ESA-T datasheet and analog systems connecting the bridge, not only requires fast, sensitive, and MAX1626ESA-T price and linearity, signal to noise ratio and MAX1626ESA-T suppliers and gain error, and so we need to meet the system requirements [1]. Therefore, the study of testing methods DAC chip, high-speed, high-resolution DAC chip R & D has very important significance.

Present, waveform measurement and analysis of association tests have been proposed technical standards DAC IEEE Std.1057, which the terminology and test methods for the DAC test provides more information. Only for traditional standard test signal generators, oscilloscopes and other test equipment, but precision is not high; large-scale chip testing automatic test equipment is used (ATE), but the cost is very high; recently proposed DAC testing methods, such as with V777 digital test system can be DAC testing, application testing analog filters for audio DAC, using digital and analog mixed-signal test system Quartet to test high-speed DAC, etc. [5], these methods in general, accuracy and cost failed to meet. To meet these requirements, proposed high-performance FPGA-based DAC chip loop test method.

1 DAC the main technical parameters

DAC is basically the main technical parameters can be divided into static and dynamic characteristics parameters parameters. DACs static characteristic parameters used to determine the accuracy of conversion, including offset error (Offset Error), gain error (Gain Error), integral nonlinearity (INL) and differential nonlinearity (DNL) and so on. DAC dynamic performance parameters to determine the performance under the conditions of its communication, including signal to noise ratio (SNR), signal noise and distortion ratio (SINAD), effective number of bits (ENOB), total harmonic distortion (THD), and no complex San dynamic range (SFDR) and so on.

2 test program

2.1 Design Principles

DAC chip parameter circuit test, the signal under test is to form a complete signal circuit. First, use the FPGA under test signal generation, after DAC chip and converted into analog signals, then through the filter, amplifier and ADC chips convert digital signals stored in the RAM in the FPGA, and then use QuartusII software tools to remove the data Signal tap II, Import Matlab software, the digital signal can be analyzed and calculated, resulting in the technical parameters of DAC [6]. Used before the ADC samples the analog signal receivers, such as oscilloscopes, spectrum analyzer, etc., can be compared with the back-end analysis of test results. Design shown in Figure 1.

The FPGA using the very flexible configuration of different programming data can produce different circuits, different resolution and sampling speed of the DAC chip can be tested parameters; filtering and signal processing circuit as much as possible to reduce the signal in the conversion and the noise transfer process; digital signal analysis and calculation is more accurate than the analog signal to ensure the accuracy of the test system; compared to other DAC test systems, components used in the test program is relatively small, relatively low cost .

Figure 1 Design Principles

2.2 Hardware Implementation

DAC with 12-bit resolution, 250 Ms / s sampling speed of the DAC chip, chip LVDS differential circuit, PTAT reference current source, and 4 +4 +4 array of key technical design to meet the high-speed high-resolution conversion circuit processing requirements. Is the Altera Cyclone III FPGA family EP3C25Q240C8 chip companies, small power consumption, systems integration capability, lower prices, including the 24 * logic cells, 594 Kbit memory space and 4 PLL, the hardware resources can meet the test requirements [8]. LINEAR ADC is the LTC2242-12 chip company, a very good exchange of properties, reducing the error caused by the test system. Op amp is the ADIs AD8008 chips, very good driving characteristics to ensure the quality of the output signal DAC chip, to improve the DACs driving ability.

2.3 software

Software code implementation using Verilog hardware description language. FPGA under test signal generation, including Test (all zero, all first-class), Ladder (ladder wave) and Sin (sine wave). Test signal which DAC chip used for testing static parameters offset error and gain error, Ladder signal used to test the DNL and INL, Sin signal for testing the dynamic parameters SNR, SINAD, ENOB, THD, and SFDR.

Data analysis and calculation process mainly through the Matlab software. Enter the all-zero DAC chip and all of a signal, calculate the offset error and gain error; using step wave signal test INL and DNL, ??in order to test accuracy, the 12-bit input data is divided into four bits of the low high school test. Parameters of the dynamic characteristics of the test DAC using fast Fourier transform method, Signal tap II Tool retrieve data through FFT and other operations, by SNR, SINAD, ENOB, THD, and SFDR parameters of the dynamic characteristics, which can fully reflect the DACs dynamic characteristics, where an accuracy of 14 order harmonics.

3 test results

Test Signal Test: DAC output of a state wide input voltage of 760 mV, enter the all-zero state output voltage of 276 uV, through the Matlab calculation, is 0.036% offset error, gain error is 3.63%.

Ladder signal test: when in the calculation of INL and DNL, ??DAC low input high four bits of each test on the same principle to the four as an example to introduce. n = 12, i change from 24 to 28, with 1LSB to represent the measured output of the 15 (Step) step wave, converted to a voltage value, part of the data shown in Table 1, each column represent the order of the data, test minimum, maximum test, test, on average, good value and to consider the effect of the final voltage low current value. Analyze the data using the Matlab software, INL and DNL curves obtained in Figure 2 and Figure 3 shows. Table 1

step wave voltage 15

Figure 2 INL curves

Figure 3 DNL curves

Sin signal test: Enter the sine wave frequency of 25 kHz, AD sampling rate of 100 MHz / s, the output digital signal through the Matlab analysis and calculation, the measured SNR is 58 dB, SINAD is 57.75 dB, SFDR is 62.84 dB, THD is 58.62 dB, ENOB 9.3 bits. Time-domain waveform and FFT, 14-order harmonic spectrum is shown in Figure 4 and Figure 5.

Figure 4 sin signal output time domain waveform

Figure 5 sin wave output frequency

4 Conclusion

To 12-bit, 250 Ms / s DAC chip, for example, based on the use of the FPGA circuit test, the test parameters of its static and dynamic parameters. Experimental results show that DAC chip can effectively test the static parameters and dynamic parameters. At the same time to test different resolution and sampling rate of DAC chip, test results than the ordinary high accuracy analog test equipment, test systems automated test equipment than a dedicated low-cost DAC.

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