Category:
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
0
1
2
3
4
5
6
7
8
9
Position:IcFull.com » IC Electronic information » Category: F

IC Electronic information

FPGA-based camera sensor interface

In Electronic Infomation Category: F | on April 13,2011

Image sensors, digital camera is an important component part. If there is no sensor, no image signal can be processed. Are not standardized, well-known sensors. In adopting the program, they have the following differences:

Conversion visible or infrared light for the way electrical signals; particularly in the signal before leaving this chip, the signal used for coding and THS4062CD datasheet and compression (sometimes) way.

Internal registers for programming the sensor means to adjust the gain, exposure time, sensor mode (such as linear, HDR), sensor image coordinates.

Way to achieve special functions, such as high (or wide) dynamic range (HDR / WDR); for example, in the same package by multiple sensors, for the same image frame multiple exposure and THS4062CD price and so on.

These sensors manufacturers to use the interface to make these electronic image signal to leave the sensor, and THS4062CD suppliers and into the downstream processing logic.

FPGA to provide a cost-effective, very small size of programmable logic platform that can easily signal from a different image sensor interface to switch to digital signals for downstream processing logic. Provide cost-effective FPGA programmable mechanisms to adapt to a variety of signal coding scheme, the register management solutions and sensor interfaces for different types of sensors to provide programmable support.

Image sensor technology

Under visible light into electrical signals used to the basic technology, image sensors can be divided into two categories. They are the CCD (charge-coupled device) sensors and CMOS (complementary metal oxide semiconductor) sensors. So far, the most shipments of CMOS image sensor is a sensor. This article is only concerned about the CMOS sensor interface.

Video processing chain in a typical application of the image sensor shown in Figure 1.


Figure 1 in the video processing chain of a typical image sensor applications Today there are several prominent

image sensor manufacturers, they are Aptina, OmniVision Technologies, Sony, Samsung, Panasonic, Toshiba and Altasens.

As mentioned earlier, sensor manufacturers configure a series of interfaces, used to leave the chip image signal transmitted to the downstream logic for processing. Very generally, the same sensor chip manufacturers need to extract according to the amount of data using different interfaces. For example, with a megapixel resolution needs of modern sensors in a given period of time came with a VGA-level resolution than just the sensor much more data. Such as high dynamic range (HDR) this requirement has also increased the amount of data required from each image frame of the image sensor to read data, and to support the smooth, low-latency high-quality video, you need at a given time from the sensor chip extraction frame, which also affects the choice of the sensor interfaces.

The evolution of the image sensor interface

So far, all sensors can be connected to the parallel LVCMOS interface, shown in Figure 2. Sensor resolution and frame rate has been increased to a level heretofore has been the mainstream CMOS parallel interface can not handle the required bandwidth.


Figure 2 LVCMOS parallel image sensor I / F

The advent of the mega-pixel sensor, the surge in demand for higher speed, HDR and support higher frame rate, the new, higher demand for speed sensor is using a different interface to overcome the limitations of parallel LVCMOS. For example, Sony and Panasonic use of sub-parallel LVDS interfaces, OmniVision use MIPI or serial LVDS. Another example is the demand to support higher bandwidth, Aptina Imaging has launched called HiSPi (High Speed ??Serial Pixel Interface) high speed serial interface. HiSPi interface can work in 1-4 serial data channels, plus a clock channel. Each signal is sub-LVDS differential signals to common mode voltage of 0.9V center. Each channel can run at up to 700Mbps under.

HiSPi bridge with parallel sensor interface requirements

Multiple sensor interface to the standard downstream manufacturers of video processing logic presents a problem because an ASSP with the support of many different sensor interface is very difficult.

Most ISP (Image Signal Processing) devices support the conventional parallel CMOS sensor interface, but usually the lack of high-speed serial interfaces. Many ISP speed parallel interface is much more than the sensor parallel interface. However, because the sensor has been relocated to a different serial interface, ISP devices need to switch to parallel interface logic. Therefore, the device will need to bridge FPGA high-speed serial data into parallel format. For video signal processing ASSP manufacturers (they have to support faster parallel CMOS sensor interface ready-made products), FPGA to solve the connection problem to the high-speed serial sensor. FPGA provides high-speed sensor and between the conventional image signal processing ASSP simple, cost-effective programmable bridge. The concept shown in Figure 3.


Figure 3 high-speed image sensor and a programmable bridge between ASSP

Bridge sensors based on FPGA reference design for serial sample

A practical example is the HiSPi Aptina Imaging for the serial interface to TI DSP parallel interface bridging, LatticeXP2-5 non-volatile FPGA to provide an efficient, cost-effective solution, shown in Figure 4.


Figure 4 FPGA-based reference design for serial sensor bridge example

The reference design with HiSPi serial interface input, the output connected to the use of TI TMS320DM3X5 Aptina sensor. * Assess the hardware has been tested Aptina the A-1000 sensor MT9M034/MTM024 and MT9J003. The reference design supports packet (Packetized) and Streaming SP HiSPi format :1-4 channel per channel running at speeds up to 700Mbps. It also simulated the parallel sensor output, the output bus width of 8,10,12,14 or 16 bits. Parallel interface can be configured as 1.8V, 2.5V or 3.3V LVCMOS level. Reference design block diagram in Figure 5.


module reference design Figure 5 Figure

FPGA on the bridge in the sensor interface challenges

Image sensor and programmable logic as a bridge between ASSP face three challenges. First, FPGA to provide interface signals to electrical signals for the support. Second, FPGAs I / O logic must have enough gearing to support rapid serial sensor interface. Third, FPGA must provide a very cost-effective small form factor to meet the modern requirements of the camera to a compact form factor.

Documents with sophisticated support for sub-LVDS LatticeXP2 non-volatile FPGA family has been proven to solve the electrical needs of the image sensor bridge. Integrated PLL, dedicated clock edge and I / O gearing logic to solve the high-speed serial sensor interface. Finally, Lattice Semiconductor (Lattice) of XP2 provides cost-effective 8 8mm area. In addition, because of its non-volatile characteristics, LatticeXP2 devices require no external boot PROM, so as to further save board space, which makes them an attractive sensor interface programmable logic platform. Image signal processing (ISP) IP makes the availability of larger LatticeXP2 devices are available in a variety of functions, such as sensor data linearization, sensor registers programmed to Bayering, defective pixel correction, gamma correction, and for each color channel up to a simple 24-bit HDR.

THS4062CD datasheetTHS4062CD suppliersTHS4062CD Price

All right reserved:icfull.com © 2010-2016 Certificate