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FPGA-based broadband Digital Channel Receiver

In Electronic Infomation Category: F | on April 23,2011

Increasingly complex environment of modern intensive electromagnetic signals, requiring electronic warfare receivers must deal with a wide bandwidth, high sensitivity, large dynamic range, multi-signal parallel processing of large amounts of information and MC34164D datasheet and real-time processing capabilities. The digital channelized receiver can not only satisfy these requirements, but also to monitor the channel to achieve the total probability of signal interception.

Digital channel wideband digital receiver, the process is the core of the widely used multi-phase filter based on digital channel of the structure. This structure first with high-speed ADC (A / D) for data sampling, the resulting high-speed data flow through the lower data rate after taking into the multi-phase filter, the filter is modulated by a prototype filter to multiple slip. Field programmable gate array (FPGA) in the rich multiplier, latch, and MC34164D price and IP core digital signal processing algorithms and MC34164D suppliers and other resources, can be very flexible wideband digital channelized receiver processing algorithms. In this paper, based on the polyphase filter structure to achieve an efficient high-speed broadband digital channelized receiver, and the companys EP3SE110F1152C4 Altera and integrated implementation, the output carrier frequency, phase information.

1 channel receiver of the basic theory

1.1 channel by

Multi-channel receiver for the establishment of real mathematical model of the signal, first of all, the number of real signal channel spectrum divided as follows:


Equation (1), k for the first k channel normalized central angular frequency; K for the division of the number of channels. Figure 1 shows the corresponding k = 8, the actual distribution of the channel spectrum. Should be noted that the actual signal spectrum is symmetric, so only four independent channels.


Real

Figure 1 Schematic diagram of the signal by the channel

Channel using the above method is not recognized by some frequency, in order to ensure that the entire bandwidth coverage without blind spots, select the channel adjacent channel by 50% overlap, that the expansion of the processing bandwidth for each channel, as shown in Figure 2 .


Figure 2 50% overlapping by the channel diagram

1. 2 polyphase filter bank structure

This paper, high-speed and efficient completion of channelized channelized receiver structure, the mathematical model shown in Figure 3.


Figure 3 high-speed and efficient digital channelized receiver architecture diagram

K for the system in Figure 3 by the number of channels, M is a multiple of each channel of the extraction and K = FM. H (n) as the prototype low-pass filter impulse response units, K a band-pass filters are generated by modulating the prototype filters, ie, uniform filter bank polyphase filter components.

K-channels output:


The introduction of multi-phase concept

available:


To wk = 2k / K into available:


Is the structure of Figure 3, the structure is in the process of channel 1 / M under the signal input rate, and can reduce the computation of the process, the systems complexity and greatly reduced data rates, real-time processing capacity is improved.

To achieve 480 ~ 960 MHz by the 16-channel, so choose K = 16. Select no blind spots adjacent channel overlap 50% of the points in the form of channel, F should be 2. According to the principle of M = 8, the signal must be taken 8 times.

2 FPGA-based channelized receiver to achieve

2.1 introduces the main chips

ADC10D1000 is the NSs new ultra high-speed low-power 10-bit analog / digital converter, single-channel maximum sampling frequency of up to 2.0 GHz, full power bandwidth of 2.8 GHz. The chip uses a single 1.9 V power supply, total power consumption of only 2.8 W, compared with the same level of A / D lower 33%, were classified as NS Power Wise family of energy-efficient products. The chip BGA package 292 of the sphere, making products more compact and lightweight, and thermally enhanced, even without the radiator, the system can also be at a temperature of -40 ~ 85 of the industrial temperature range. The chip spurious-free dynamic range (SFDR) up to 66 dBc, the industrys highest level, and the effective number of bits (ENOB) of up to 9.1, to enhance the dynamic range of wideband digital receivers to provide a strong condition.

ADC10D1000 with 8-bit high speed A / D compared to the number of performance has improved, but the maximum analog input voltage peak value of 860 mV, compared with 8-bit high speed A / D low, making the input signal 3 dB of power should be below recommended the following when the power is 2 dB.

Selected StratixIII series EP3SE110F1152C4 models FPGA. The series combination of FPGA is the worlds best performance, maximum density and lowest power 65-nm devices. Has the lowest static and dynamic power consumption, faster than the previous generation of devices by 25%. Stratix III FPGA family has 338,000 logic elements (LE) and 27 million registers, with 17.2Mb of 600MHz memory and 896 18x18 multipliers. Stratix III FPCA supports more than 40 I / O interface standards, support for high-speed core and high-speed I / O, has achieved 400 MHz DDR3, and has the industrys best signal integrity.

2.2 Hardware Design

Hardware design block diagram shown in Figure 4.


Figure 4, the hardware design block diagram

A / D conversion is the prerequisite for digital processing, and its performance directly affects the overall performance of the receiver. The performance indicators are sampling rate and resolution. RF front-end output signal of the center frequency of 720 MHz, bandwidth of 480 MHz, based on bandpass sampling theorem, the required A / D sampling rate of the device should be 960 MHz. To get a large dynamic range of the receiver, the required A / D resolution of the device should be as small as possible, the output data bits as possible. Above two points selected ADC10D1000.

Order to ADC10D1000 provide a more stable and better phase noise clock signal, the clock signal by an external crystal oscillator and PLL (LMX2312 and VCO190-964) generated. VCO190-964 in the frequency range 951-977 MHz, single-ended output. Controlled by the FPGA works LMX2312 and the operating frequency, the design phase to monitor use compared to 200 kHz frequency, LMX2312 clock signal by comparing the self-generated feedback signal with the VCO control voltage, locked VCO output frequency is 960 MHz.

ADC10D1000 input requirements for the differential form of the clock signal, and therefore through the transformer ADTL2-18 Dui VCO output signal conversion, and the transformer should be connected to the output impedance 100 differential A / D input impedance. A / D output to LVDS signals, so in connection with the FPGA 100 termination resistor should pay attention to is closer to FPGA pins. To ensure ADC10D1000 output diminished

Less data throughput, designed to increase the internal 1:2 Demux data width of the approach, that same 10-bit parallel output sample data group 2, and DDR mode both rising and falling edges of the clock method of reducing the output data clock rate , the output clock frequency down to 960 MHz clock signal is 1 / 4, that is 240 MHz.

In order to debug, you can easily change the internal FPGA signals to determine the magnitude of the threshold, without waiting for a long time FPGA compilation, add in the design of DSP. DSP code can correct phase establishing the zero phase difference.

2.3 FPGA application

Software modules including digital channelized data output sorting process and the follow-up of two parts. Digital Channel mainly composed of the mathematical modeling, including: data extraction, symbol conversion, polyphase filtering and IFFT. Subsequent data processing of the main results obtained according to the channel frequency and phase information and the three-way signal at the same time to reach judgments. FPGA internal processing block diagram in Figure 5.


Figure 5 FPGA block diagram of the internal processing module

2.3.1 data extraction transformation

A / D sampling the output of the 240 MHz high-speed differential signal into the FPGA. According to the above model, if the number of channels K = 16, then taking multiple M = 8, FPGA via serial LVDS interface and to convert an 8-fold extraction. Designed using Quartus of LNDS module complete signal and convert the string to reduce the signal and clock rate. Design will set INDS receiver module form, select the 8 times the conversion factor, we can get the output signal of 16 groups and and A / D of the clock synchronization with the way the 60 MHz clock. Global clock with the clock-driven follow-up as all the processing modules. Because A / D sampling in offset binary output signal types, subject to change module symbols into the binary complement type.

2.3.2 polyphase filter design and simulation

Polyphase filter bank with a stable system, can achieve linear phase FIR digital filter. FIR filter design prototype sampling frequency of the main considerations fs, pass-band ripple rp, rs stop band attenuation and transition bandwidth. For example, with fs = 960 MHz, rp = 0.1 dB, rs = 63 dB, transition zone starting frequency 15 MHz, the cutoff frequency 30 MHz, the prototype filter frequency characteristics are shown in Figure 6 curve. The low-pass prototype filter order of 192 bands, the prototype filter is divided into 32 phases, each phase of 6-order filter. As a result of 50% of the insert overlapping structure at an interval of zero-phase filter for each order to 12 bands. Designed to use multiply-accumulate operations to achieve programming FIR filter. Prototype FIR filter coefficients are generated by MATLAB export, quantified the filter program writes FPGA.


Figure 6, the prototype filter amplitude-frequency characteristic curve

2.3.3 IFFT operations

IFFT operation at the time selected by the base -2 algorithm. To speed up the signal processing speed, IFFT module using multi-stage pipeline design and operation of the macro module generated by Quartus. For example, the core of IFFT operations by Altmult_complex butterfly macro for macros and lpm_add_sub. Each complex multiplication takes four 18x18 DSP multipliers, so the single channel occupancy of the IFFT totaling 136 multipliers.

2.3.4 Channel Output

Because the input is real signal, obtained by the IFFT 16-channel sub-band signal. For each channel using rotation digital computer algorithm (CORDIC) calculated for each channel signal amplitude and instantaneous phase. Based on CORDIC output signal amplitude and signal to determine whether there is signal the start and end points, given the corresponding pulse envelope. CORDIC output phase while taking advantage of the instantaneous phase difference method based on frequency. In order to improve the accuracy of frequency measurement, the pulse rising edge after 4 consecutive stable without phase ambiguity average frequency measurement, the output carrier frequency coding. CORDIC with two-channel signal output phase estimates the phase difference of two-channel signal, the output phase encoding.

External interfaces in order to save resources, a maximum output of three-way three-way signal that different signals simultaneously, when a road channel pulse occurs when the envelope of the channel frequency code and phase code output, or do not output. 16 channels should be judged, to determine whether the output. Specific processes shown in Figure 7, when the judge not to set up or end of statement execution, end the program.


Figure 7 to determine the output of the logic flow chart

3 system hardware simulation and result analysis

Completed the design EP3SE110F1152C4 channel two-channel process, pulse output signal envelope and the carrier frequency, phase information is encoded output. Simulation in hardware verification, the use of the embedded logic analyzer - SignalTap Logic Analyzer. It is a debugging tool that can capture and display real-time signal characteristics in the FPGA, FPGA through the JTAG interface to download and upload configuration data captured signal data, and the computer signals observed in FPGA internal nodes, allowing users to work throughout the design process speed in order to observe the system-level hardware and software interaction. FPGA chip, the consumption of resources as shown in Table 1 occupy 82% of total resources, including SignalTap LogicAnalyzer occupied resources.

Table 1 FPGA chip, the consumption of resources


A / D sampling accuracy directly affect the accuracy of the back, so first A / D performance testing. RSN signal peak signal to noise ratio is defined as the point of zero frequency and the power and remove the first five post-order harmonic component of all the noise power ratio. Signal to noise and distortion ratio SINAD is defined as the peak point of the signal power and after removing all zero-frequency harmonics and noise power ratio, the value smaller than the signal to noise ratio. Spurious free dynamic range SFDR is defined as a single signal input signal with the largest harmonic or spurious power ratio.

First experiment: the grounds of the input signal frequency signal generated by Agilent 83752A sine wave frequency of 720 MHz, amplitude -1 dBFS, sampling frequency is 960MHz, derived from the FPGA, the sampling data for 8 k point FFT, was signal spectrum shown in Figure 8.


Figure 8 A / D output 720MHZ signal spectrum

The calculated SNR RSN is 47.5 dB, signal to noise and distortion ratio SINAD is 46.3 dB, the effective number of bits ENOB is 7.4 bits, SFDR spurious free dynamic range is 59 dBc.

Experiment II: Using Agilents E4438C vector signal generator as a frequency input, the input carrier frequency of 725 MHz, PRI = 10s, PW = 2s pulse signal test results shown in Figure 9. Figure 9 in the first line of the input signal through the LVDS output waveform after deceleration, the middle 15 rows of 15 channels that envelope pulse output, the penultimate line of the envelope indicated that one output pulse output carrier frequency code, the last line of that a pulse output of that envelope all the way to the phase difference between the output code.


Figure 9 Output interface

From the above analysis, the carrier frequency of 725 MHz signal should appear in the 705 ~ 735 MHz of channel 9, the output carrier frequency code is 725-480 = 245, DSP writes the output of the phase difference correction code encoding 0. Can be seen from Figure 9, there is only the first 9-channel pulse envelope, the output carrier frequency code is 245, the output of the phase code is 0, which is consistent with the theory.

Experiment three: use Agilents E4438C vector signal generator as a frequency input, the input carrier frequency of 725 MHz, PRI = 10s, PW = 2s pulse signal. IF simultaneous acquisition with an oscilloscope input pulse signal and pulse output signal envelope can be obtained carrier frequency code and phase code output delay time, the delay time of the test results the entire system shown in Figure 10. A line above the input of the IF pulse signal, a line below the signal envelope for the output pulse, the system can be seen from Figure 10, the delay time is less than 1.3s, the system ensures real-time processing.


system delay time Figure 10

Experiment Four: Agilents E4438C with a vector signal generator and two IF input as Agilents 83752A, respectively, the input carrier frequency 510MHz, PRI = 100s, PW = 10s; carrier frequency of 720MHz, PRI = 90s, PW = 8s; carrier frequency of 930 MHz, PRI = 80s, PW = 20s pulse three-way. Three-way acquisition with an oscilloscope pulse output signal envelope signal, the system can be the result of multiple signal processing shown in Figure 11. The top of the line for the first pulse output interfaces enveloping Road, in the middle of the line for the second pulse output interfaces enveloping way, way below the line for the third envelope pulse output interface. When the signal overlap in the time domain, the output from different output pulse envelope; or in the first output interface output. It can be seen from Figure 11, the system reaches the same time completed a multi-signal processing.


Figure 11 the results of signal processing systems and more

4 Conclusion

This paper, engineering, completed a 16-channel 960MHz digital channelized receiver FPGA. Polyphase filter with high-speed digital channels of the structure of efficient implementation of digital channel receiver, can ensure the wide instantaneous bandwidth requirements, while maintaining the purpose of real-time processing; and traditional channels of digital hardware structures to save resources and improve the system overall job performance. FPGA simulation results show that the model implemented in the FPGA on the feasibility and practicality of, and requirements to achieve the desired targets.

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