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Position:IcFull.com » IC Electronic information » Category: F

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FPGA-based FIR filter design and implementation of efficient

In Electronic Infomation Category: F | on April 18,2011

Abstract: The paper presents a FPGA-based digital filter design methods. The method first by MATLAB to design a FIR filter with specific indicators, and DCP010512DBP datasheet and then the filter coefficients are processed to make it easy to implement in the FPGA, and DCP010512DBP price and then distributed algorithm based on CSD code filter structure and DCP010512DBP suppliers and design, to avoid the multiplication operation, saving hardware resources, the pipelines design approach also improves the speed. Matlab and Modelsim simulation shows that the design functions correctly, can achieve rapid filtering.

0 Introduction

Digital filter in the voice and image processing, pattern recognition, radar signal processing, spectral analysis applications, has an important role. It can not be overcome by the analog filter to avoid the drift and noise problems, while more than analog filters and high precision, good stability, small size, more flexible, and therefore widely used. In acoustic logging, the usually accurate filtering of signals, and the filter has strict real-time requirements. In this paper, Matlab design tools supporting design of a FPGA-based logging and can meet the needs of high speed digital filters.

1 linear phase FIR filter structure

Many different types of digital filters, the classification method is also different. The unit from the digital filter impulse response point of view, finite impulse response digital filter into digital filter (FIR) and infinite impulse response digital filter (IIR). Compared to IIR filters, FIR filters can be precisely linear phase design, and quantify the structure of a stable filter coefficients. Treatment for acoustic logging in with the requirements of acoustic signals of linear phase, FIR filter is preferred.

In the time domain, FIR filter input and output process is a unit impulse response of the input signal and the linear convolution of the process, the differential equation expressed as:


Where, y (n) is the filter output, x (n) for the sampled data, h (n) for the filter tap coefficients. The structure shown in Figure 1 (a) shows, the figure, N-1 N-order FIR filter coefficients to use description, usually requires N multipliers and N-1 two-input adder can be achieved. Not difficult to find the coefficient multiplier is just the coefficient of transfer function, therefore, the structure and is called direct-type structure.

For the coefficient of symmetric FIR linear phase filter can be equation (1) rewritten as follows:


Improved FIR filter coefficients symmetrical structure shown in Figure 1 (b) below. The structure of the coefficient of symmetry (the same or opposite) of the tap further multiplication after the merger, it will give half the number of multipliers reduced to the original, but adds an additional adder.


Figure 1 FIR Filter Structure

2 design methods and targets

FDATool is dedicated Matlab Signal Processing Toolbox filter design and analysis tools, the tools main role is to extract the filter coefficients in accordance with design specifications. Digital filter design using FDATool filter type is the key, window function, filter order, cutoff frequency and other parameters of choice. Window function which is used to determine stop-band attenuation and transition bandwidth, commonly used window functions are rectangular window, Hanning window, Hamming window and Blackman window. Rectangular window and Hanning window lower stop-band attenuation, and Blackman window of a larger transition zone, relatively speaking, more in line with the design requirements Hamming window, which can reach the minimum stopband 54.5dB, the normalized bandwidth of the transition zone 3.11 / M (filter order N = 2M +1). For acoustic logging signal, the design should be the parameters listed in Table 1.

Table 1 filter parameters


Figure 2 shows the filter magnitude and phase frequency response curve, the curve is maintained in the linear phase passband, stop-band attenuation greater than 52dB, transition zone bandwidth is 1.65kHz. Tap coefficients can be quantified in the toolbox for the fixed-point integer data in order to achieve order in the FPGA 127 of the filter, the filter coefficients of a total of 128. For larger filter order, its stop-band attenuation and to quantify the impact of transition zone is minimal.


Figure 2 the amplitude and phase frequency response curve

3 FPGA-based filter design FIR filter design with FPGA

The key is how to deal with the resource-intensive multiplication unit. Distributed algorithm (DA) of the proposed multiplication can be converted to shift add operation, thus saving hardware resources. If the order for the filter coefficients Hk, xk (n) is n times the sample input, y (n) is n times the system response, then the equation (1) can be equivalent to the following formula:


The data provided the source data format is 2s complement form, there are:


Where, xkb (n) as a binary number, it is desirable value is 0 or 1; xk0 (n) as the sign bit of 1 indicates that the data is negative, 0 indicates that the data is positive. Therefore, (4) into (3), we have:


Equation (5) is called a distributed algorithm. It can be seen in square brackets represents the input variables of a data bit and all the filter tap coefficients H0 ~ HN for every one "and" operation and summation. The index shows the sum of the results of some of the right bit, integer multiplied by 2b is left b bits, which can be achieved through hardware connections, without taking the logical resources. This can be achieved through the establishment of a lookup table operation in square brackets. Lookup table can be used with all input variables are addressed one, which is distributed algorithm based on look-up table (LUT-DA).

LUT-DA algorithm look-up table size is B 2N bits, where B is the input data bit width, N is filter order. As the filter order increases, the lookup table size is 2, exponential growth; when B is 16, N 128, the lookup table size has been unthinkable. Therefore, the lookup table into multiple sub-tables, can effectively solve this problem, which also gives rise to more effective serial LUT-DA algorithm and parallel LUT-DA algorithm, but both are inadequate. For the serial structure, to complete a output, requires multiple clock cycles is greater than B; and the parallel structure, although you can complete a one clock cycle output, but the need to copy the table LUT B were identical, and this will increase the hardware resource overhead.

To both speed and area, the paper design of a DA algorithm based on the principle of CSD-DA algorithm. First, the coefficient of equation (3) of the fixed coefficients Hk after the commencement by a power of 2 can get:


And then swap the order of the shift and accumulate, you can get the following formula:


Where, Hkb value of 0 or 1 is the weight coefficient; Sk 1 that Hk is positive for -1 indicates that Hk is negative; skb the value of the desirability of 0, -1 or 1. After (4) the commencement of multiplication will be converted to shift all the add operation in which the weight of the part can be removed to 0 without making calculations. To further reduce the Hkb nonzero entries in the array can be encoded Hk CSD code, from the least significant bit binary code starting with 10 * * * 01 to replace all greater than or equal to 2 1 serial, 1 This bit is -1. CSD said one of the two in any adjacent, must contain a 0, so the largest number of no more than 1 N / 2. On average, CSD said that with about 1 / 3 of the bit is nonzero, which complement that less than about 1 / 3 of the non-zero bits. Suppose h = (15) 10 = (01111) 2, y = hx = x (23 +22 +21 +20), and if the (15) 10 encoded as (10001) csd, then, Y = x (24 -20). Binary encoding, will use three adders, but with the CSD code, only used a subtractor, we can see, CSD coding can essentially reduce hardware overhead. Optimized through the CSD code, skb the number of non-zero value will be far less than the number of non-zero values ??Hkb.

Coefficients for linear phase FIR filter is symmetric, in order to reduce the multiplication unit, choose the structure shown in Figure 3. Since all multiplications can be transformed into a large number of addition and subtraction, so the critical path is too long will cause the system to run slower. Register to join the line, you can reduce the critical path length, thereby improving the system maximum operating frequency. B were constants in, skb the number of non-zero value of the uncertainty, it is the time during the pipeline design can be flexible according to skb segmentation, the longer the path, add more pipeline registers. In order to prevent overflow of intermediate results, to have redundancy bit wide registers, for a number of symbols, the bit width value for the M + log2N-1, M for the higher-bit-wide accumulator, N is filter order.


Figure 3 lines CSD-DA algorithm local structure

Water from Figure 3 the structure optimized CSD-DA algorithm can be seen, all the multiplication will be converted to shift addition, shift operations can be hardwired implementation, the entire structure of the pipeline after a reasonable segmentation.

Table 2 is the combined result of different filter structures. Parallel structure which is the worst kind of structure, it takes a lot of resources, slow; serial LUT-DA structure, though they take less resources, the maximum operating frequency is high, but that is a serial structure can not be completed in one clock tick filtering operation of a sampling point; and pipeline CSD-DA structure is in terms of speed, or area, have obvious advantages. If the working clock is 75MHz, then beat a clock output can complete a deal with 330 sampling points in the single channel signal only 4.4s, to meet the requirements of real-time logging.

Table 2, the combined result of filter

4 Analysis

Order to verify the correct function of the filter can be in the design of the simulation in Modelsim. If the original waveform with the noise of the acoustic signal, then the results of the filter shown in Figure 4.

Figure 4 in the filter in the Modelsim simulation results

Figure 5 shows the filter in the Matlab simulation results, we can see, Modelsim and Matlab simulation results. In the frequency domain, compared to Figure 5 (a) and Figure 5 (b) can be seen, the filtered waveform 5kHz ~ 18kHz retained only part of the spectrum, which shows the structure of CSD-DA line digital filter design is correct.

Figure 5 in the filter in the Matlab simulation results

5 Conclusion

This paper describes the tool through the Matlab FIR linear phase filter design methods and design for the acoustic signal than the traditional structure of the pipeline CSD-DA structure, which has obvious advantages of speed and area. The article also confirmed by simulation of the design is reasonable and correct. But it is worth noting that the structure is only suitable for fixed filter coefficients of the occasion, but if you want to make changes, you need to re-encode and CSD coefficients pipeline division.

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