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FPGA + DSP-based radar speed data acquisition system

In Electronic Infomation Category: F | on April 27,2011

Abstract: Laser radar echo signal by transmitting spread to the formation of optoelectronic devices convert electrical signals with a pulse width, low amplitude, background noise and LM337KC datasheet and other characteristics of its existing low-speed data acquisition data accuracy not high. Meanwhile, A / D converter and LM337KC price and digital signal processors connected directly lead to data transmission in time, affect the system reliability, real-time. Back signal for the laser radar is proposed FPGA and LM337KC suppliers and DSP-based high-speed data acquisition system, the use of FPGA internal asynchronous FIFO and DCM to achieve A / D converter and the DSPs high-speed external memory interface (EMIF) between the data transfer. ADC peripheral circuits are introduced, and the DSPs EMIF timing of work setting parameters, and simulate asynchronous FIFO read and write data, combined with detailed analysis of the hardware structure design should pay attention to. System sampling rate of 30 MHz, the sampling accuracy of 12 bits.

0 Introduction

Radar data processing technology with the rapid development requires high-speed acquisition radar echo signal. However, the launch spread of laser radar echo signal converted by the optoelectronic devices to form a pulse width of telecommunications, ranging from low, and background noise, such as the use of low-speed data acquisition system for the collection, there are not high accuracy of data. Meanwhile, in order to avoid the data transfer is not timely, data loss, affecting the reliability and real-time systems, need high-speed data acquisition system design and development. Design for the front-end output

about -25 ~ 25 mV, 20 MHz signal bandwidth, high bandwidth, low noise, high data transfer rate, high-resolution digital-analog conversion chip AD9235; use XC2V250 size within 6 KB implementation of asynchronous FIFO between TMS320C6201 AD9235 converters and high-speed data transmission. Acquisition system sampling rate 30 MHz, resolution 12 bits, internal asynchronous cache FIFO as 6 KB, meet speed data acquisition requirements.

1 system design

If the A / D directly to the external memory interface with the DSP EMIF connection, will the overloaded DSP, on the other DSP peripherals need to expand, with a sampling input shared external bus, for external devices to read and write, does not allow data collection has always been occupied by the external bus. If you can not receive data in a timely manner, the last stored data will be overwritten, causing data loss. Asynchronous FIFO can achieve data transfer in different clock domains, it can be used as A / D converter and a bridge between the EMIF, each piece of data is written, it will notify the EMIF removed from the FIFO data. Based on the above analysis, Figure 1 shows the block diagram of high-speed data acquisition system.

Figure 1 high-speed data acquisition system block diagram

FPGA DCM as the internal A / D converter and DSP to provide the sampling clock and an external oscillator, A / D converter and DSP operate in different clock, the FPGA internally generates an asynchronous FIFO as data cache. A / D converter to sample the value of write FIFO, FIFO write enable WR_EN has been effective, the system power on, A / D converter has been in working condition, every written piece of data Bianxiang DSP interrupt signals the interrupt read FIFO data. FIFO input data width of 12 bits, the output data width is 24-bit, FIFO read clock is higher than the write clock, DSP read the data than the A / D to the FIFO write data faster, and faster DSP internal data processing time can ensure high-speed real-time system acquisition.

2 A / D converter circuit

A / D converter circuit is an important part of the whole system. On the front end output of about -25 ~ 25 mV, 20 MHz bandwidth digital RF signals, designed with ADC chip AD9235, the maximum sampling rate of 40 Mb / s, 12 bit data output, SNR RSN = 70 dB. AD9235 is a differential input, single-ended signal input needs A / D driver chips, the choice of low-distortion differential A / D driver chip AD8138, Figure 2 for the A / D converter, AD9235 analog input set 2VPP, the internal reference voltage VREF 1 V reference voltage, and also as a driver chip AD8138 common mode voltage. Using AD8138 input signal amplification, magnification RF / RG = 2.49 k/820 3. Hence, the AD8138 single-ended differential conversion and amplification input signal range 25 ~ 175 mV.

Figure 2 A / D converter circuit

3 FPGA Interface Design

3.1 Clock Design

With 30 MHz external crystal is used as the clock source, use the internal clock manager XCV250 DCM, respectively, for the AD9235, the asynchronous FIFO, TMS320C6201 provides clock source. DCM CLK0 output of the AD9235 30 MHz clock as the sampling clock and asynchronous FIFO write cycle WR_CLK.

Using DCM digital frequency synthesizer output CLKFX as TMS320C6201 clock source. Formula: DCM output CLKFX frequency = input clock CLKIN frequency (M / D), take M / D = 5 / 3. This DCM to provide 50 MHz clock for the TMS320C6201, after 4 octave, DSP system clock is 200 MHz, external storage EMIF clock CLKOUT1 to 200 MHz. CE0 space control register to set the parameters, so that FIFO Read Timing SETUP, HOLD is equal to a CLKOUT1 cycle, STROPE equal to two CLKOUT1 cycle time sequence shown in Figure 3, when reading the first number, EMIF automatically to maintain the minimum 2 clock cycles The establishment of the time, follow-up data read, create time for one clock cycle. FIFO read clock cycle of about 50 MHz, compared with A / D FIFO write data to the fast time to ensure the system real-time acquisition.

Figure 3, FIFO data read timing

3.2 Asynchronous FIFO Interface Timing

AD9235 with FPGA Interface design should carefully consider ADC conversion clock, FIFO write clock and selected intermediate logic devices timing and delay characteristics to ensure correctly set sampling clock. AD-9235 sample data in the sampling period delay after 7 in the data line, Figure 4 A / D with FIFO Interface Timing.

Figure 4 A / D with FIFO Interface Timing

Read FIFO operation, using EMIF external memory control signal, includes: output enable bit and the read and the external space to enable chip select signals. Literacy timing Figure 3, output enable and external space chip select signal low, asynchronous FIFO read enable RD_EN effective, when Reading enable bit as low, pending read data initialize will then jump high, rising edge asynchronous RD_CLK side, this time in an asynchronous FIFO data is read out. Figure 1 HALF_FULL bit directly with TMS320C6201 external storage regional interrupt EXT-INT5 trigger connection, when FIFO cache reached semi full, rising edge trigger DSP external interrupt, DSP start DMA (direct data storage) to burst way read FIFO data , to read the clock CLOCKOUT1 FIFO to store data. EMIF FIFO read and logical relationship;. Figure 5 is an asynchronous FIFO

simulation diagram, the input data width of 12 bits, the output data width is 24 bits. Reading the clock is set to 50 MHz, write clock is 30 MHz.

asynchronous FIFO simulation of Figure 5 Figure

4 design should pay attention to the problem

If the asynchronous FIFO FULL signal as interrupt source, full signal bit FULL valid start trigger DMA transfer, DMA transfer in between full signal and, A / D acquisition clock is still driven A / D converter, will cover collection of data previously stored, resulting in data loss; the use of a HALF-FULL flag signal for the signal, half-full when the DMA transfer start, do not interrupt data acquisition, the A / D EMIF read write speed than the speed, nor result in data coverage.

FPGA internal asynchronous FIFO data bus data bus connected with the TMS320C6201, TMS320C6201 should pay attention to data acquisition and bus access conflicts between peripheral. Should ensure that there is no prolonged occupation of the external data bus equipment, or cause loss of data collection.

5 Conclusion

For the radar echo signal, FPGA and DSP design is based on high-speed data acquisition system, introduced the radar front-end signal A / D converter peripheral, the use of DCM and asynchronous FIFO to achieve high-speed ADC and data buffer between the DSP to ensure that effective transmission of data collection. System sampling rate of 30 MHz, 12-bit sampling accuracy, asynchronous FIFO memory buffer size is 6 kbits, can meet the requirements of high speed acquisition. FIFO and the DSP uses 24-bit data interface, read the FIFO using DMA data transfers more full use of DSP resources, real-time processing to improve the capacity of the system.

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