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FPGA + DSP-based Multi-Serial Data Communication

In Electronic Infomation Category: F | on April 19,2011

Abstract: The serial port used in the FPGA and AD7859AS datasheet and DSP based signal processing board and AD7859AS price and the structure of the exchange of data between external devices. The GPS RTK positioning based on the application for a single serial port full-duplex transmission at the same time not to respond to multiple input and AD7859AS suppliers and output data types case, designed and implemented a multi-serial port for different types of data transmission scheme. The program by adding a single serial control registers to control all the serial interrupt signal, the use of ping-pong continued rapid alternating read and write data input. Independent tests show that the program can be configured for each port, which can achieve the results of GPS positioning, differential GPS correction data exchange with the outside world and user control command input, and hardware debugging time can be reduced, saving on hardware resources.

Universal asynchronous receiver / transmitter (UART) is a universal serial data bus for asynchronous communication, can achieve full duplex communication. UART IP core is used in the external device and the Atera FPGA chip serial communication between SOPC an implementation. It can replace the RS-232 to achieve chip peripheral input / output (I / O) operations.

GPS RTK (Real Time Kinematic) can provide centimeter-level real-time positioning solution. During dynamic positioning, the base station will accurately known GPS coordinates and observation data passed to the rover in real time using microwave links in the rover in real-time differential processing, base station and the station coordinates are poor; coordinate differences with baseline coordinates of each point by the rover station coordinates. Base station receiver to provide information to end users include GPS satellite clock, ephemeris data, the user pseudorange and carrier phase measurements of parameters such amendment.

Signal processing used in this paper plates can be used as a GPS RTK base stations, base station network with other positioning to receive differential correction data or their own high-precision single point positioning and differential correction output data mapping results. As the base station, not only accurate positioning information in real time output, but also differential data exchange with the outside world. As the same time requires a lot of continuous differential data input and output and user input control instructions, designed with three serial ports.

1 Hardware Structure

Signal processing board for the FPGA + DSP structure, with multi-channel A / D, D / A conversion device. IF signal by the A / D sampling to be completed after the carrier into the FPGA, PRN code correlation operation, IQ transform DSP chip or other operation carried out by the position resolution. User input through the serial port control instructions choose serial port GPS positioning results of GPS differential correction data output and input and output.


signal processing board block diagram of Figure 1

FPGA chip configuration of the three serial ports, respectively, UART0, UART1, UART2, assigned by the SOPC Builder corresponding memory space and interrupt request mapping. Each module uses the default base address, and were set UART0, UART1, UART2 data input interrupt request number for IRQ1, IRQ2, IRQ3. In addition, DSP chip may at any time through the three serial port to send different data.

If the DSP to send data on each port, are issued to the NIOS II CPU interrupt request, you will need 3 PIO pins, pins take up too much resources. The realization of the program by adding a serial port control register, only with a PIO pin.

The same time, and interactive control DSP chip signal distribution PIO interrupt request number is IRQ0.

Each UART port has input, output, two RAM as a cache, the data bit width is 16bits. Among them, the serial input buffer named ReadFromMemInterface, serial output buffer named WriteToMemIntedace (see Figure 2). Note that the actual transmission data, the serial port parameters of the external device data bit length is set to 8 bits, so the software needs to deal with the word serial and byte conversion.


Figure 2 NIOS II CPU address map

Figure 3 is in the NIOS II CPU in Quatus connection diagram, which is located in the center inst6 module. The CPU primarily pin as defined in Table 1.


Figure 3 NIOS II CPU in the connection diagram Quatus

Table 1 CPU main pin definition


Is worth noting that, ts_clk input clock 20.46 MHz clock frequency is the NIOS IICPU, serial baud rate 115 200 bps, the clock frequency can be obtained. DSP6713 the EMIF is 32-bit bidirectional input and output, in this part of the design of the serial port to use only low 16 bits, using the three-state gate to control data flow. Three-state output enable gate input signal is given by ce space dsp enable signal ce_6713.

Serial input data is written first by NIOS II CPU input buffer for each serial port, when to meet the conditions issued by the out_pio interrupt pin to the dsp, to inform their corresponding serial data can be read, the cached data from the dspread0 three states passed the door when the tri-state gate tri_16.dsp read input direction for the dsp, dsps EMIF data lines evm_D data appears, with the EMIF address lines evm_A serial input data to complete the transfer to the dsp; when there is data to dsp The serial output, the data from the dsps EMIF data lines evm_D input, dsp by in_pio issued to the NIOS II CPU interrupt signal, the request to send data. Send and receive process detailed below.

2 Software Design

NIOS II CPU of the control code part of the points-based interrupt response functions and various functions. Register in the main function to complete initialization, the serial data output task. Serial port interrupt response function is mainly to complete data entry tasks. FPGA and DSP

order to facilitate the exchange of information between the control, each port has a fixed length of each address is 32 bits (4 bytes) of input and output two control registers. Through reading and writing of the flag of the serial port can be realized control system. Serial port input control register defined in Table 2, the output control register is similar.

The user to control instructions (including the signal processing board configuration parameters, the output data type of control, etc.) and the differential correction data, data length and data continuity is very different, in addition to conventional data transmission additional data on each port block transfer mode. Block transfer mode can be used for continuous input of large amounts of data, with each port of the two ping-pong RAM read and write operations to the program implementation. Block transfer mode is used by the serial port control register in the first 14-bit (P_flag) decision. For non-cached data block size of the input mode of routine data need to set the maximum length, is too small will result in some data loss. When data needs to be output from the DSP to the NIOS II CPUs RAM to write the output of the UART control register settings, and to issue an interrupt through the GPIO signals. In the NIOS II CPUs main function is to set a loop to check if the input of the interrupt signal from the DSP, and then test if the output of the UART control register. Output flow chart shown in Figure 4.


Figure 4 serial data output process Figure 4 SET_EN

for setting a serial input mode (if the input and the ping-pong ping-pong input buffer size) and serial port to enable other operations, the input control register in the system initialize the default values ??written by the DSP .

When the data input, NIOS II CPU detects the interrupt request from the serial port into the corresponding interrupt response program. First, the data transfer mode to judge, P_flag default value is 0, indicating non-data block input mode. The model input data has a specific combination of the end identifier, once detected, mark the end of the cached data is sent and received completion status is cleared for the next time; P_flag compared to a continuous block of data input, which when Half_BAM0 or Half_RAM1 filled immediately when a DSP interrupt signals, DSP enters the interrupt service routine reads the data. Program flow chart shown in Figure 5.


Figure 5 flowchart

3 Conclusion

Altera FPGA chip using the NIOS II CPU control on the serial port has the advantage of full use of hardware resources, can reduce the computational DSP chip. Tests show that, NIOS II CPU operating frequency of 20.46 MHz, the serial port baud rate is set to 115 200, the data bits to 8 bit, the serial input and output simultaneously normal. Can input and output of serial data transmission by the mode of instruction can be flexibly configured to suit the needs of different types of data transmission.

This article addresses the single serial port can not meet the high precision GPS receiver, while a variety of data input and output requirements, implement the results of GPS positioning, RTK real time differential data exchange with the outside world and user control command input. The advantage of this program by increasing the serial input / output control register, so that DSP chip can be had only two GPIO resources to achieve the required three serial input / output functions corresponding to the six interrupt operations; using NIOS II CPU multi- serial control can reduce the hardware debugging time, saving resources within the FPGA chip. The downside is that unrealized serial baud rate, data bits and other real-time configuration.

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