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Embedded Design cable fault detector

In Electronic Infomation Category: E | on April 22,2011

Cable communications, test and MAX148AEAP datasheet and other important carrier signal transmission system, with the increased number of cables and MAX148AEAP price and running time, more and MAX148AEAP suppliers and more frequently the cable failure. Concealed cabling and test equipment limitations, so that the cable is very difficult to find fault. This paper presents a Nios embedded processor core of the cable fault detector, application of A / D device and FPGA composed of variable-frequency high-speed data acquisition system, the use of low-pressure pulse reflection method to achieve the principle of the cable circuit, short circuit , circuit point, short circuit detection and localization. The instrument can be widely used in communications maintenance, construction and cabling, and telephone cable, coaxial cable and other barriers to testing and maintenance.

1 System Architecture

Low voltage cable fault detection pulse reflection method. The main principle is: to send a voltage pulse to the cable, when the firing pulse encountered in transmission line failure, due to the fault point impedance mismatch, resulting in reverse pulse, by calculating the time difference between the two T, and analyze the characteristics of reflected pulse Identification and fault location. This method is suitable break, bad, low resistance or short circuit test.

Fault distance L is: L = V T / 2. Where, V is the pulse propagation velocity in the cable. According to the reverse polarity pulse to determine the nature of failure: broken or poor contact caused by reverse pulse is positive, low resistance or short circuit fault caused by the reverse pulse is negative.

The instrument is a portable cable fault detection equipment, use of modern electronic technology (such as high-speed A / D technology, the asynchronous FIFO technology, field programmable gate array FPGA, etc.) to improve integration and flexibility. Overall structure of the system shown in Figure 1.


Figure 1 System Architecture

Pulse detection circuit to generate pulse, high-speed A / D converter and its reflection on the pulse echo signal is sampled, the use of asynchronous FIFO as the A / D sampling data cache. Soft-core Nios as the core of the system to control the start and end detection tasks, the choice of pulse sending and receiving mode, A / D sampling data processing computing, fault and determine the nature and location of the display. Among them, the soft-core processor and logic functions are programmable logic devices in the field of programming.

2 function and performance

Short-circuit test: detection of electric cables is unnecessary connection between their locations.

Circuit test: detection of a cable wire is open circuit and its location.

: Displays the test results, which measure the open circuit and short circuit position.

Measurement range: 2 ~ 1000 m.

Test accuracy: 2 m and 10 m select two accuracy.

Pulse amplitude: load open 5 V.

Pulse width: 20 ns, 100 ns.

Maximum sampling rate: 100 MHz.

Waveform record length: 1024 points.

3 Hardware Design

To Alteras FPGA device EP2C20 Cyelone II family as the core functional use of its Nios soft core microprocessor designed and completed the relevant circuit. Custom programming FPGA devices through the pulse, high-speed clock and high-speed data storage FIFO module such as a basis for the design of pulse circuits and high-speed transmit and receive data acquisition and processing circuits.

3.1 Microprocessor Systems

Simply, Nios is a processor IP cores, designers can put it in the FPGA. Nios soft core processor is a backbone pipeline RISC general purpose microprocessor, the clock signal frequency up to 75 MHz. Flash used to store boot code and applications, when the system is reset or when power up, Flash the boot code will be executed. SDRAM memory using the applications executable code and data, provide operating space for the program. Nios soft core with Flash and SDRAM, connected to the FPGA, the design shown in Figure 2.


Figure 2 Nios soft-core with Flash and SDRAM, connected to the FPGA, the design

3.2 probe pulse generation

Used for fault detection pulse width 20 ~ 100 ns, FPGA clock work up to 200 MHz, in which the generated pulse down counter can be produced to meet the requirements of the pulse signal. Subtraction counter produces pulses of amplitude limited FPGA operating level, the detection is not enough, so come out from the FPGA to go through the square wave pulse amplification, detection can be coupled to the cable to go. SN74LVC4245A for level translation. sta and pulse_input are from FPGA. This design uses a 5 V pulse amplitude, pulse feed to the transistor emitter-driven approach. This drive is relatively simple for the device will be more.

3.3 A / D converter circuit

Detection pulse width 20 ~ 100 ns, the corresponding data sample rates between 20 MHz and 100 MHz change in the general A / D chip is difficult to meet the sampling requirements, and use multi-chip A / D chip cost and design are more difficult. NS companies here use the United States ADC08100, its sampling rate is 20 ~ 100 Msps, this time as sampling of the power 1.3 mW / Msps, Sampling power will increase as the sampling clock, but the characteristics of the sampling will not be affected Therefore, the sampling rate in a variety of system chips can play the role of multiple chips. According to the different sampling rate, by a clock control module to produce the corresponding sampling clock signal to the chip work at the required rate under both cost savings and can simplify the design. ADC08 100 and the FPGA with the use, you can easily change the sample clock, with great flexibility.

A / D converter circuit shown in Figure 3. Probe pulse and the echo signal to be converted into a suitable A / D chip, the signal voltage level and then sampled. Pulse in the input op amp was clamped before treatment, using two sets of inverted diodes in parallel, to avoid excessive breakdown pulse amplifier.


Figure 3 A / D converter circuit

3.4 clock signal generation

Detection pulse generation, ADC08100 sampling, data caching and asynchronous FIFO, constitute a high-speed A / D data acquisition system. This is the time for a variety of signals with demanding, require specialized unit to match the clock to make the circuit under the right timing. In the FPGA, the clock module can be easily customized to generate A / D sampling clock, asynchronous memory read and write clock, and clock pulse counting module. All the clocks are made of a high-speed clock synchronization, and the entire system is synchronized with a start signal to run under to ensure the samples timing requirements.

3.5 Power Module

System, both analog circuits have high-speed digital circuits, the use of power type of complex, there is +5 V, +3.3 V, +1.2 V, -5 V power supply and other signals. In the circuit board design is necessary to reduce the production of high-frequency digital signal on analog signals of electromagnetic interference, but also to avoid interference between the various power, so plan to be a reasonable layout and wiring to the module to improve the signal stability.

4 Software Design

FPGA software design includes the development and application, application design, and LCD driver design.

4.1 FPGA development and application

Field programmable logic device FPGA (Field Programming Gate Array) with high density, high speed, low power, powerful, and so on. In this system, the companys CycloneII using Altera devices to achieve high-speed data acquisition, storage, software in QuartuslI 7.1 VHDL hardware description language used to design completion. High-density programmable logic device design process, including: design preparation, design input, design process and device programming in 4 steps, and the corresponding functional simulation (before simulation), timing simulation (after simulation) and device design verification test 3 .

This design, including Nios processor, pulse generation, high-speed clock and high-speed data storage FIFO and other modules.

4.2 Application Design

Application control the start and end detection tasks, the choice of pulse sending and receiving mode, A / D sampling data processing terms, failure to determine the nature and location and results output.

5. Conclusion

This paper, based on Nios soft-core cable fault detector design. Pulse Reflection Method for the concrete realization of failure was proposed based on field programmable logic devices, high-speed sampling system design, and on this basis, a comprehensive system design. Simulation and experimental results show that the system can realize the cable circuit, short circuit fault detection, with online monitoring, the advantages of easy control, and flexible and a good extension.

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