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Embedded DSP chip to access low-power design of SDRAM

In Electronic Infomation Category: E | on April 14,2011

DSP chip with limited memory capacity allows designers are often stretched, especially in the digital image processing, speech processing and dtc143zka datasheet and other applications, the need for high-speed large-capacity storage space, strong support. Therefore, the need for external DSP memory to expand storage space.

DSP-based embedded applications, the memory system has become the main source of power. For example, Microns MT48LC2Mx32B2-5 chips, the maximum power consumption during read and dtc143zka price and write can reach 924 mW, while most of the DSP core power consumption is much less than this value. Such as TIs TMS320C55x series of core power consumption only for the 0.05 mW / MIPS. Therefore, optimization of storage systems embedded DSP power consumption is extremely important design goals. In this paper, to access the external SDRAM as an example to illustrate the external storage systems reduce power consumption design.

1 SDRAM Power Source

SDRAM is generally divided into multiple storage within the body, through the rows, columns, time-multiplexed address, the system address bus body on different pages of different storage units addressing the specific storage. SDRAM memory bank are two of each state, that is activated and dtc143zka suppliers and turned off. After the first read and write access, maintain store activation status as an open page policy (open-page policy), the page register saved in the address line has been opened, until it had to be closed, such as the refresh command to be executed, etc.; After the store closed access to the body as a closed page policy (close-page pol-icy).

Order to better decision to choose which strategies need to be familiar SDRAM power consumption. SDRAM power consumption of the main three sources: activation of closed storage body, read and write, and refresh. In most programs, the activation caused by power off memory bank deposit accounts for the operation to visit more than half of the total power consumption. Figure 1 shows the read and write to the same SDRAM row, the use of open page policy and close page policy compare the power consumption (assuming a consumption of active power off memory bank 1), the calculation shows that if a few consecutive a read and write operations on the same line, the use of open page policy can save power consumption.


open the page in Figure 1 closed page policy and strategy for the power comparison

SDRAM power according to the characteristics of the face analysis shows that to minimize the activation of on / off power stored in the body caused by the additional overhead, is to optimize the SDRAM memory system, the fundamental power, the other can not be ignored has been active with the storage body to the power consumption.

2 low-power SDRAM access optimization design

For better management of external SDRAM, most of the embedded DSP chip integration and external memory interface EMIF (External Memory Interface), DSP EMIF chip devices to access and manage memory. The same line by the EMIF will merge together to read and write as much as possible, reducing activation of on / off power stored in the body caused by the additional overhead. Figure 2 shows the incorporation of bus-based design of monitoring programs to read and write the block diagram.


Figure 2 bus-based monitoring program designed to read and write merging block diagram

1) using the block method of reading instruction fetch. Adding simplified instruction Cache (I-Cache), SDRAM will be read by the read process block. Only in Cache miss, by the Cache through the EMIF for SDRAM to block read, read 16 bytes each.

2) by adding after the write data buffer (WPB, Write PoST Buffer), the request will be sent on the data bus to the WPB, the block by the WPB on the SDRAM write, read and write merging.

3) EMIF bus, dynamic monitoring of the utilization of block read and write merging strategy used page open when the bus utilization is low, the use of a closed page policy, when the bus utilization is low, the SDRAM into sleep mode.

3 access SDRAM low-power design

3.1 read by block I-Cache

Read for the program bus, according to the procedures of the locality principle, the next time to get instructions and the current instruction to fetch is likely in the space adjacent to, so for the reading program uses the block method of reading, each read a block, not a word, and an open page policy, so read and write operations on the same line does not require additional activation of on / off operation can be completed faster.

When the instruction on-chip memory in, you can use the CPUs instruction on the most recent I-Cache, the view of improving overall system performance and low power design requirements. DSPs I-Cache size is designed to 8 KB, including 2 memory, the structure of the same, each piece is structured as follows:

1) data queue, each queue contains 256 lines of 16 bytes. When I-Cache miss, we will use least recently used algorithm (LRU) replace the long time use of the line.

2) significant bit queue lines, each line has a line valid bit, once the full line of data. To set the line valid bit.

3) label the queue, each line has a label field, the data show that the row start address. When a line fill, the corresponding tag will be deposited into the bank of the tag field.

If you want to take the instruction word in the I-Cache (the hit), I-Cache will be sent directly to the DSP. If you want to take the instruction word is not in I-Cache in the (missing), I-Cache through the EMIF will read from the external memory interface 4 32 b of the code block. Once the instruction word is read in the I-Cache to give CPU.

3.2 buffer after writing the design

Data storage location in memory space that may not be as a continuous process, and the data space read and write, read and write to the SDRAM data space to optimize the basic idea is to merge the same line of SDRAM read and write operations. Specifically, including the merging of multiple read the same line, merge on the same line multiple write operations, merging of multiple read and write the same line 3 cases, the literature of this design approach is proposed, the basic idea is: the system from the pre-fetch buffer (FB, Fetch Buffer) in taking data; write data, the first to write merging write buffer (WCB, Write Combine Buffer); FB or the WCB in the same row in the read and write requests to merge. However, this design method is targeted at a general microprocessor system Cache, too complex, too costly to achieve, not suitable for data of this study is not a Cache of the DSP, so this write-back buffer (Write Post Buffer) approach, the specific design methods are as follows:

1) write in the EMIF after the establishment of a buffer, all of the SDRAM read and write requests are sent to the write back buffer, write buffer immediately after the response to the CPU, CPU can not wait for the end of the write operation to continue program.

2) whenever the write buffer is received after the written request of a new, first determine the existence of after-write register and the write operation in the SDRAM write the same line, if so, merge the two write operations write to the SDRAM after the same time.

3) When the CPU read the data, first check the write back buffer, if there is to read the data directly from the read-after-write data buffer; if there is, from the write buffer after the current read operation in the selection and write the same line, after merging, the SDRAM read and write operations. After the write buffer

design process can not only enhance the efficiency, but also can save power consumption. Considering the system performance and power requirements, where after the DSP write buffer is designed to 8 KB, and the I-Cache with a similar structure.

3.3 dynamic monitoring bus utilization

SDRAM in all lines open, read and write operations waiting for all the lines when the power is off more than 2 times, so low-power SDRAM to the needs of design have joined the sleep mode. When a large number of read and write the same line when they need to adopt an open page policy, keep these lines open. Taking into account these features of SDRAM, a separate page with an open or closed page policy strategy is not appropriate, require a combination of use. Monitoring EMIF bus utilization, block read, block write and read and write merging strategy used page open when the bus utilization is low, the use of a closed page policy, when the bus utilization is low, the SDRAM to enter hibernation mode when necessary Che live.

An example to MT48LC2M32P2 power estimation, assuming the same line before and after two visits to the probability of hit is 90%, when the bus utilization (each cycle the number of bus is the average utilization) is higher than 25%. The open page policy strategy than using a closed page to save power, when the bus utilization rate of 25% to 20%, the use of two strategies is not very different strategies used to maintain the current, when the bus utilization is less than 20 %, the use of a closed page policy strategy than using an open page to save power, when the bus utilization rate of less than 10%, in the use of a closed page policy, while the end of each visit will be SDRAM into sleep mode, compared simple strategy of using closed more economical power consumption of the page.

Document statistics generic processor bus utilization of different procedures, as shown in Table 1. Can be seen, for different procedures, bus utilization varied. Based on the current utilization of the bus to decide which strategy is more appropriate to access SDRAM.

Table 1


4 EMIF optimized performance analysis

Monitoring of the bus used to read and write programs to calculate merger, assuming the same line before and after the hit probability is 90%, calculated based on Micron data sheet, merge the two write operations 24% reduction in power consumption, bus utilization for different The results shown in Figure 3.


Figure 3 merge bus-based monitoring program to read and write power consumption calculation

5 Conclusion

DSP-based embedded applications in systems, storage systems, power system power consumption accounted for the majority. When the external memory is SDRAM, the lower line breaks SDRAM access can save a lot of power. This design merge bus-based monitoring program to read and write, not only reduces the power of external storage systems, and to a certain extent, improve storage system performance. I-Cache can be added to make the program faster reading instruction bus, after joining the write buffer (WPB) can make the CPU do not have to wait for the slow end of the external write operation directly to the implementation of instructions.

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