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Digital IF-style design of the spectrum analyzer resolution bandwidth

In Electronic Infomation Category: D | on April 14,2011

Spectrum analyzer in a realization can be divided into two kinds of analog and LT1036CT datasheet and digital, the former based on the analog filters, digital filters and LT1036CT price and the latter based on FFT analysis. In contrast, analog spectrum analyzer can not get real-time spectrum, and LT1036CT suppliers and the analog filter will be nonlinear, drift and aging effects, measurement accuracy is not high; the digital spectrum analyzer based on digital filters because of its and therefore a small form factor, frequency, high resolution, good stability, the analysis can get very narrow bandwidth, and high precision; and because it is based on high-speed ADC technology, digital signal processing, FFT analysis, design, and thus has a variety of spectral analysis. With the field-programmable gate array (FPGA) devices, DSP devices, and other logic in the chip size and processing speed so rapidly improve performance, digital spectrum analyzer to measure the speed, real-time is also stronger.

Type in the digital IF spectrum analyzer, the resolution bandwidth filter is designed for digital IF processing module key, which determines the effective signal bandwidth of spectrum analysis, and characterization of the spectrum analyzer clearly separated in the response capacity of the two input signals , the spectrum analyzer is one of the major technical indicators. In order to meet the real-time signal and accuracy requirements, usually high-speed A / D sampled digital IF signal, but its data rate is too high, so it becomes the bottleneck of digital processing. Generally need to use the digital quadrature demodulation to baseband signals Banyi, and then through a multi-rate signal processing techniques to design a decimation filter to reduce the data rate, the ultimate digital FIR filter.

This paper, digital down-conversion technology, and FPGA-based hardware design of digital IF processing module, called a different IP core design, while using the structure parameters can be configured to implement a variable resolution bandwidth filter and the extraction rate of digital filters . The IP core is a rigorous performance testing and optimized timing stability, and therefore satisfy the system of high-speed and real-time processing requirements.

1 digital down conversion principle

All-digital IF processing software radio technology is one of the key technologies, which are mainly used in the IF signal down conversion to baseband signals, while reducing the sampling rate, the technology needed to ensure that the signal can not be mixed stack, which is very convenient in the follow-up more baseband signal processing technologies. All-digital IF technology including digital quadrature demodulation techniques and multirate signal processing techniques in two parts.

1.1 digital quadrature demodulation

Also known as orthogonal frequency demodulation, which is mainly realized through the digital mixer, set the input IF signal is:


Where the center frequency of the signal is much larger than signal bandwidth B, and the signal sampling rate to meet the Nyquist theorem, that f0>> B, fs> 2B. Then, after the orthogonal transformation, the signal baseband modulation signal is:


Where, ZBI (t) called the I signal, ZBQI (t) called the Q signal. From (2) can be seen, baseband signal ZBI (t), ZBQI (t) contains only the amplitude and phase information and the frequency is zero, so the process is from the IF quadrature demodulation signal x (t) to obtain the baseband signal process.

Quadrature demodulation process modules for the orthogonal two-channel structure, are called I and Q channels channels. Since the input and quadrature local oscillator, mixer by the digital implementation, it has a high integration, consistency and good, can get very good channel uniformity, but also makes use of digitally controlled oscillator phase has also been the orthogonality a good guarantee.

1.2 Multirate Signal Processing

IF signal due to the higher sampling rate, while the baseband signal processing generally just under the lower sampling rate, therefore, the digital quadrature baseband signal after demodulation are in a state of serious over-sampling must be carried out sampling rate conversion between the data stream to reduce the rate of change of this signal sampling rate is based on multirate signal processing technology.

Multiple extraction can reduce the sampling rate integer multiple of the signal, the extraction ratio for the D. Extract reduced the signal sampling rate, so after taking the signal may no longer satisfy the Nyquist sampling condition aliasing. In order to ensure that the desired signal is not distorted, taken before the general use of digital low-pass filter first taken after the sampling rate according to the signal band-limited treatment, so that the filter cutoff frequency c for the maximum bandwidth required for signal B, When the sampling rate before extraction, after extraction sampling rate fs1 and fs2 meet fs2 = fs1 / D 2B, the signal does not produce aliasing after extraction.

1.3 extraction rate of more than the spectrum analyzer filter theory

Digital IF-type spectrum analyzer resolution bandwidth is the multirate filter design through implementation. For even after over-sampling down-conversion of data streams, you need to filter and extract at different rates in order to obtain real-time analysis of different bandwidth. Thus, the actual extraction rate varied greatly, for example, when you need a narrow resolution bandwidth, its extraction rate is high, requiring a multi-level filtering and extraction to gradually reduce the sampling rate, this also reduced for each level anti-aliasing filter requirements. Since ADC is sampling frequency, data rate and sampling rate are the same, while the FIR filter can not guarantee that the design of bandwidth, high sampling rate, therefore, first through the CIC (comb filter) and HB (half-band filter ) filter extractor to extract a large, fast down the data rate, and then filtered by the FIR filter. With quadrature demodulation, digital down conversion block diagram shown in Figure 1.


Figure 1 Block diagram of digital down-converter

CIC (comb) filter coefficients are 1, and only addition operations, and there is no multiplication, so hardware implementation is very easy, and can achieve a high processing rate, it is suitable for the extraction system in the first stage decimation and the large extraction factor. However, the transition zone of a single-stage CIC filter and the stopband attenuation is not good, usually used to increase the multi-stage cascade filter sidelobe level attenuation. Selected five cascaded, the stop-band attenuation of about 67.3dB, to meet the requirements of the first stage filter attenuation. Although the CIC decimation rate is higher, but its frequency response 3dB bandwidth is very narrow effective. And to ensure the effective bandwidth is essentially the same, and continue to reduce the extraction rate, followed by level half-band filter can be used.

HB (half-band) is almost half of the zero filter coefficients, the filter computation time can be reduced by half. While the extraction factor is fixed at 2, so that after N-level HB filter, you can reduce the sampling rate of 2N times. Multi-stage filter frequency response after taking the pass band without overlap, only the intersection of edges in the transition zone, which has good anti-aliasing effects.

Through the CIC filter and the filter HB multiple extraction, base-band signal is reduced to a lower sampling rate can be suitable for FIR treatment.

The high order FIR filter can be designed into the transition zone is small, stop-band attenuation and has a good form factor with high frequency response to meet the spectrum analyzer resolution bandwidth filters for special requirements.

2 digital IF processing logic

In recent years, FPGA logic devices in technology and scale of the rapid development and continue to lower costs, the use of FPGA devices to achieve high-speed professional digital down converter module system design has become a common method. FPGA chip, which integrates a large number of programmable logic resources, but also contains a wealth of hard-core digital signal processing and solid-core resources, so the system can meet a variety of digital applications and design, and the IP core is rich in resources, to implement flexible fast, stable performance, high-speed timing requirements to meet.

FPGA IP core is pre-designed modules, the general parameters of the structure can be configured, and can be called Core Gener-ator tool. The design of digital down conversion can be numerically controlled oscillator quadrature digital demodulation (NCO) and the multiplier, respectively, call the IP core DDS Compiler 4.0 and Multiplier 11.2 to achieve, which DDS Compiler provides two channels SINE and COSINE. The decimation filter design, shown in Figure 1 can be multiple sets of filters by calling the IP core (CIC Compiler 1.3 and FIR Compiler5.0) to achieve. CIC Compiler 1.3 can provide input data sampling rate, frequency, and programmable settings for various parameters such as extraction; HB filters and FIR filters are used FIRCompiler 5.0, the IP core can import *. coe format filter coefficients, and through the introduction of different factors to distinguish between different types of filters. It also provides a set of different types of filter structures, including the multiply-accumulate structure, based on the DA algorithm and polyphase filter structure and input data sampling rate and frequency parameters of the basic filter set. DDC

the overall design of the module shown in Figure 2, the I, Q two asymmetric, for convenience, here only describe the Q path realization of digital down conversion. This design uses Xilinxs Spartan-3A-DSP series FPGA chip implementation, which integrates DSP48A module, and rich in multipliers for the realization of digital signal processing module, and the cost and power consumption are very low.


Figure 2 the overall design of digital down converter module

Processing module principle by digital down conversion can be followed by quadrature demodulation, decimation filter and FIR filter, finally get the baseband signal. The module has three inputs, the signal input for the A / D converter output sequence, the median 14-bit, sampling rate of 100MSPS, center frequency of 21.4MHz, which determines the median digital IF in the NCO output is set to be the same 14-bit, the output frequency is set to 21.4MHz.

Clock input is the A / D converter output sequence with the way the clock frequency of 100MHz, the work can be used as processing module clock.

In the ISE FPGA design platform in, BUFG is a global buffer, which is connected to a dedicated clock chip resources, to reduce signal transmission delay and improve driving skills, which is the key for the timing circuit is a clock signal very important. DCM is a digital clock management unit, with minimal clock delay and jitter, so the method can be used DCM + BUFG assigned to FPGA clock input clock. Global clock resources can be used to ensure that the timing synchronization. Bandwidth of the input for the resolution bandwidth

step input, which determines the bandwidth to be analyzed B (RBW) and filter extraction. Operation, the first may be the last one to be analyzed to determine the bandwidth FIR filter 3dB bandwidth and the input sampling rate, and then under the A / D sampling rate and the ratio of FIR input sample rate to determine the CIC filter and the HB filter stage extraction factor United series.

In addition, the overall design of the module, the median deal is also a key, it is determined by the bandwidth of step input, adjust the various parts of the binary output bits wide. Because for the convolution filter multiply-accumulate operations, which will lead to an increase in the median filter output can be output to meet the precision and accuracy required in the circumstances, and each level of the quadrature demodulator to do after the median filter processing This method first in order to prevent redundant output digit level in the post-filter additive, thus saving FPGA logic resources; the second is to adjust the filters output amplitude, different bandwidth options to avoid inconsistencies in the output amplitude.

3 resolution bandwidth design

The design of the resolution bandwidth range from 1kHz ~ 3MHz, 1-3-10 by step transformation, a total of 8 stalls. Step input, such as resolution bandwidth listed in Table 1, were determined for each step the corresponding CIC cascade extraction factor and HB series, but also determines the final level of FIR filters and the corresponding input data sample rate.

Table 1 extraction factor allocation table (sampling rate of 100MSPS)


Decimation filters purpose is to post high-speed quadrature demodulation baseband signal to the proper signal rate reduced to common baseband processing technology used. In this setting, the baseband signal sampling rate and resolution bandwidth of 5 times between steps in order to calculate the corresponding I, Q baseband signal sampling rate, and to determine the total extraction rate of processing module. Extraction rate of the IP core parameters can only be an integer, so the ideal extraction rates to take on the whole, should try to meet the RBW and the base band signal proportional to the sampling rate. The stalls for the low extraction rates, only the extraction can be completed by CIC, but on the HB filter bypass control, that is, taking cascade HB 1. Through the filter bypass control and extraction of factors extracted programmable to achieve a wide range of adjustment factors, and thus control the data stream sampling, analysis bandwidth can also change the sampling rate control.

Shown in Figure 2, the overall design of the diagram, CIC filter is to extract the part of the first level, enabling high-speed extraction, but the pass band, stop band characteristics of the control is not strong. Set extraction rates approved by IP (R) and series (N) and other parameters, and simple operation.

HB filter is to extract the part of the second stage, single stage decimation factor is fixed at 2, 3 and 5 cascading cascading two conditions are used at all levels of normalized frequency design methods, to avoid duplication design. Usually the FDATOOL MATLAB tools to design filters, and RBW filter the input signal sampling rate of 2 times the reference frequency as a normalized, while ensuring the FIR filter pass-band frequency range of signals without attenuation. The FIR filter passband is set to 0.2, and the HB filters as a decimation filter in this major, it set a maximum pass-band frequency 0.21, filter order of 19 bands, as shown in Figure 3 is a half-band filter devices (HB) of the frequency response curve. Symmetric half-band filter coefficients and the coefficient of nearly half of the coefficient of zero, 19 filter coefficients only 6 in multiplication, they will not consume a large amount of multipliers, the other to extract part of the I, Q data flow rate of two higher, so the use of the structure built by accumulating HB filter to meet the processing requirements of high-speed timing.

Resolution bandwidth in the design of each step input corresponding to the RBW filter, FPGA logic in order to save resources and simplify the design, you can also use normalized frequency design methods, this could make I, Q branch of the design of a RBW filter. Since the input sample rate FIR filter fs greater the higher the order the minimum filter, which select the 3dB bandwidth and sampling rate according to the normalized ratio of 0.2 to design the filter frequency response, and the FIR filter without taking , the input sampling rate is equal to I, Q baseband signal sampling rate. According to I, Q signals of the normalized bandwidth of 0.20 can be set RBW filter passband frequency limit of 0.20, stopband frequency limit of 0.29, the order of 47-order filter, stopband attenuation is 60dB, the waveform factor SF60 / 3 = B60dB/B3dB = 0.29/0.20 1.45, as shown in Figure 4 FIR filter frequency response curve.

Format of the generated *. coe filter coefficients can be called into the FPGA, IP cores, FPGA multiplier taking into account the limited resources, the input data collected by the front, the data rate has decreased DA-based algorithm used here structure to build RBW filter.


Figure 3 half-band filter (HB) Frequency response


Figure 4 resolution filter (FIR) frequency response

4 Conclusion

Using FPGA IP core hardware and call all kinds of all-digital IF technology to achieve the application method, the timing performance and stability, can satisfy high-speed, real-time signal processing requirements. The spectrum analyzer resolution bandwidth design, combined with the range of 1kHz ~ 3MHz analysis bandwidth can be programmed, can be used multirate signal processing technology to reduce the sampling rate of digital signals, and digital amplitude / phase detector, video detector, DSP development, and The subsequent realization of FFT frequency spectrum analysis preparation. The digital IF processing module can also be used in network analysis, traffic analysis, radar signal analysis and other design, and can reduce the system size to ensure the reliability of the design.

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