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Crystal stability study on the impact of IEEE1588

In Electronic Infomation Category: C | on April 12,2011

Abstract: a better use of IEEE1588 precision time synchronization protocol, time synchronization interval to predict, according to IEEE1588 time synchronization principle, analyzes the factors that affect the accuracy of time synchronization, a detailed study of the crystal stability of time synchronization accuracy impact. Get an accurate analytical expression, and NE521N datasheet and derived the analytical expression based on an analysis to determine the size of synchronous time interval. By measuring the actual project, show that the theoretical analysis and NE521N price and actual measurement results are consistent with a good practical value.

0 Introduction

With the development of electronic technology, time synchronization technology are becoming increasingly widespread. IEEEl588 precision clock agreement (the PrecisiON Time Protocol referred to as PTP), is a network for precision clock synchronization protocol. It is widely used in measurement and NE521N suppliers and control system, the time synchronization master and slave device technology. The agreement can be accurate for the system time synchronization, the synchronization sub-microsecond time accuracy can reach orders of magnitude, and may achieve higher time accuracy.

In IEEE1588 synchronization protocol, time synchronization accuracy is subject to the primary communication path from the device asymmetry and the amount of crystal stability. The master and slave of the crystal stability of the difference is the main reason for the accuracy of time synchronization.

The quartz crystal manufacturing processes and their oscillation, even the same batch of the same company produced the same type between two quartz crystal oscillator frequency error also exist. As the frequency of quartz crystal frequency drift and the inevitability of errors, so the stability of the crystal on the IEEE1588 time synchronization accuracy is very practical application value.

1 IEEE1588 time synchronization principle

IEEE1588 time synchronization process is through the master and slave devices to pass each other with a time stamp of the master and slave signals to calculate time offset between devices, enabling time shift compensation.

Figure 1 shows the time between master and slave device time synchronization process. Need a synchronization between master and slave devices communicate 4 times (4 times the message transmission), by the time stamp message exchange of information, from the master device can be calculated from the time offset between devices.

From the device was t 1, t 2, t 3 and t 4 four time information, you can get the following formula:


Where, tms that t 2 and time interval between t1; tsm that t4 and the time interval between t 3; tmean _ path _ delay _ ms said master device to the path delay from the device; tmean _ path _ delay _ sm said the device from the device to the main path delay; toffset said master clock from the clock and the time between the offset.

From (1), equation (2) can be:


Equation (1): t m that the updated time from the clock; tm that is not updated with the deviation from the clock time.


Figure 1, the clock synchronization principle

Instability of the crystal and the transmission path delay and other causes of asymmetry in the time between master and slave devices offset is cumulative over time.

A specific time in order to ensure accuracy, the synchronization process requires a specific time interval to be repeated.

2 factors affect the accuracy of time synchronization

From (3) can be drawn, the clock offset of the two factors. The first factor is the main transmission path from the delay between devices t mean _ path _ delay _ sm and t mean _ path _ delay _ ms uncertainty in the accuracy of time synchronization; second factor is the master and slave device to pass the time between information t 1, t 2, t 3 and t 4 the error of time synchronization accuracy.

2.1 Path delay analysis

From the main equipment for fixed, between the main transmission path from the device is fixed. In practice, the path delay tmean _ path _ delay _ sm and tmean _ path _ delay _ ms can be measured by one-time, at a fixed master-slave system, the path delay due to the IEEE1588 protocol time precision error is negligible The. In the non-fixed master-slave device, path delay changes that would make a serious impact on the precision time synchronization. The analysis here assumes that the transmission path is symmetric, ie:


To (3) can be simplified to:


Time information

2.2 Error Analysis

Time information t 1, t 2, t 3 and t 4 the error is mainly caused by two factors: the time information received for the sampling clock phase error and the master and slave device crystal stability.

Sampling clock phase error is inevitable impact of the so-called sampling clock phase error is not aligned along the sampling clock (phase error) caused by the different sampling points. And cause the time information t 1, t 2, t 3 and t 4 of the error. Although the sampling clock error is inevitable, but it caused by the accuracy of the synchronization time of the maximum error is only one clock cycle, the high-speed clock, this error can be negligible.

Master and slave device caused the crystal stability of master-slave synchronization is an important factor in the clock error is determined by the physical properties of the crystal determined by the hardware. The following study will focus on the factors of in-depth analysis and research.

3 of the crystal stability of the IEEE1588 synchronization accuracy Electronic equipment

crystal reference clock count the clock that is usually the way through the count to achieve. In the IEEE1588 synchronization protocol [8], the main equipment of the crystal from the difference in stability of time synchronization accuracy is the main factor, the crystal frequency and frequency offset directly determines the size of the time synchronization accuracy.

Master and slave device consists of two different crystal oscillator reference pulse, so the master and slave devices inevitably there is a crystal oscillator frequency error f.

3.1 crystal between master and slave device error of

If a crystal frequency f, the frequency stability is . Then the actual frequency can be expressed as:


Between two devices used in the crystal, according to the following derivation to get the error between the two crystals.

Function f (x, y) = x-y, at the point (x 0, y0) and ignore the higher the start there:


Equation (7), f is the variable x and y after the operation the function f (x, y) in (x0, y0) at the error.

Master and slave crystal oscillator used in the index is assumed to be: the master oscillator frequency f10, the frequency stability is 1; crystal oscillation frequency from the device f 20, the frequency stability is 2. Master and slave device crystal frequency can be expressed as:


(8), (9) into the type f (x, y) = x-y, and then the f (x, y), f10, f20, 1 and 2 were brought into the (7 ) where the f (x, y), x0, y0, x and y. The resulting frequency error between the two crystal f is:


Master and slave devices are usually equal to the crystal frequency, so that f 10 = f20 = f 0, there are:


3.2 crystal length of time interval error of synchronization constraints

Under Part 2 master and slave device time synchronization process analysis, the time between master and slave device synchronization process is carried out periodically. How to stability of the crystal to determine the maximum synchronization period in order to achieve both master and slave devices can satisfy the precision requirements of time, but also the synchronization process to minimize the communication bandwidth is occupied by the following to study.

Master and slave clock pulse count is usually the way to achieve the time synchronization process, the master clock is synchronized reference clock, it does not need to correct for loss of generality, assume that the master clock is absolutely accurate, Therefore, from the clock error analysis is obtained in Section 3.1 (11) of f.

Master clock count value is expressed as Cm (t) = f1 t, from the clock count is expressed as Cs (t) = f2 t, the time from the clock count offset:


By the analysis of Section 3.1 between the main crystal from the device error (11) into (12) can be:


Each count, the time required from the device for the first time the crystal oscillator 1 / f0, so by the time the clock count from the offset is very easy to get the time from the clock offset:


Assuming each of the synchronization process

time interval T0, be brought into the equation (14), master and slave devices can be obtained by the crystal produced the greatest accuracy of the time from the clock offset:


4 Conclusion

Laser warning device in a master-slave devices, IEEE1588 precision time synchronization protocol has been successfully applied, the device uses the same type of two crystals: frequency 100 MHz, frequency stability of 5 10-6 . Each time interval synchronization process using 50 ms. To the above data into equation (15) obtained from the device produced by the crystal oscillator accuracy of the time from the clock offset: 0.5 us. The experimental measurement of the actual time offset from the device is 290 ns or 300 ns. Through equation (15) is offset by the time the crystal stability under the maximum deviation to obtain the actual stability of the crystal in the studio is a random value, so the actual measured data in the maximum time within the scope of the offset is right in line with the results.

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