CPLD serial interface circuit design

A hardware circuit design ALTERA CPLD is used

this company EPM240T100, combined with serial communication MAX232 interface chip design, block diagram shown in Figure 1.

Figure 1 CPLD serial communication module hardware design

II, VHDL design and STAC9766T datasheet and description of program modules

Using VHDL on the CPLD programming, design three modules, the baud rate generator module, receivers, transmitters.

1. Baud Rate Generation Module

Baud rate generator is actually a divider, as mentioned earlier, the paper design of the baud rate of 19.2kb / s, designed to use the clock frequency of 10MHz, so the counter counts to 260 to turn when the count turn.

Procedure is as follows (the key part of the reservation, non-essential part of the place by ... ...):

... ...

ENTITY uart IS

GENERIC (d_len: INTEGER: = 8);

PORT (

F10MHz: IN STD_LOGIC; - the system clock

Reset: IN STD_LOGIC; - reset signal

Rxd: IN STD_LOGIC; - serial receiver

Txd: OUT STD_LOGIC; - Serial transmission

);

END uart;

ARCHITECTURE behav of uart IS

... ...

BEGIN

Rxds <= rxd;

PROCESS (f10MHz, reset)

- Set the baud rate generator 19200kb / s

VARIABLE clk19200hz: STD_LOGIC;

VARIABLE count: INTEGER RANGE 0 TO 260;

BEGIN

IF reset = 0 THEN

Count: = 0;

Clk19200hz: = 0 ;

ELSIF f10MHzEVENT AND f10MHz = 1 THEN

IF count = 260 THEN

Count: = 0; clk19200hz: = NOT clk19200hz;

ELSE

Count: = count +1;

END IF;

END IF;

Baud_rate <= clk19200hz;

END PROCESS;

2. Transmit module

T_state send some programming using the state machine, a total of two values: t-start and STAC9766T price and t_shift, respectively, start to send and STAC9766T suppliers and send hold. Reset button is pressed is set to t-start state, and transmit data bit is set to "1" bits of data sent count is 0, the t-start state, the state machine will be in this state and wait for the baud rate count rising edge of signal level. Rising edge arrives, according to the different values ??of the state to do t_state different treatment, if it is t-start start state is first read the data to be sent, and send start bit "0", and then send the state to maintain a t_shift state, sending remain t_shift state, continue to send the data to determine whether the full 8 bits, if the full state of the regression t-start, or continue to send, keep t_shift state, in order to avoid interference with the status of the remaining cases, automatically jump to the t- start state. Procedures are as follows:

PROCESS (baud_rate, reset, data)

- Data transmission part of the

VARIABLE t_no: INTEGER RANGE 0 TO 8;

- You send the data bit number

VARIABLE txds: STD_LOGIC;

VARIABLE dtmp: STD_LOGIC_VECTOR (7

DOWNTO 0);

BEGIN

IF reset = 0 THEN

T_state <= t_start;

Txds: = 1 ;

T_no: = 0;

ELSIF baud_rateevent AND baud_rate = 1 THEN

CASE t_state IS

WHEN t_start =>

Dtmp: = data;

Txds: = 0 ; - Send Start

T_state <= t_shift;

WHEN t_shift => IF t_no = d_len THEN

Txds: = 1 ; - Send end of the

T_no: = 0;

T_state <= t_start;

ELSE

Txds: = dtmp (t_no); - send a byte of data

T_no: = t_no +1;

END IF;

WHEN thers => t_state <= t_start;

END CASE;

END IF;

Txd <= txds;

END PROCESS;

3. Data receiving module

State machine used to receive part of the program, a total of two states:

R-start and start receiving r_shift and receiving, respectively, hold; reset button is pressed to set the r-start state and store the data received data to be assigned to "00000000" in the r-start status, receive state machine will be in this state and wait for the baud rate counter rising edge of signal level. Baud rate rising edge of the module count, based on the state to do different treatment of different values, if it is r-start the state is waiting to start receiving start signal, detected rxds = 0 start bit signal to maintain good reception to r_shift state, r_shift receiver will continue to hold the received data to determine whether the full 8 bits, if the full return of r-start the state, or continue to receive, maintain r_shift receiving hold, in order to avoid interference with the status of the remaining cases, automatically Jump to start receiving r-start state, a similar procedure and send the parts, here omitted.

Three serial communication program VHDL simulation results Serial Port Communication

simulation results shown in Figure 2. It can be seen from the figure, each transmitted byte, or 8-bit data, the line will output a high level, then began to send the next byte.

Similarly, the simulation waveform shows that the data reaches the receiver pin rxd effective before the line is held high until you receive a low start bit, after the start bit, 8-bit data serial receiver in order to save the results after the signal data received of you.

Figure 2 Serial communication simulation waveforms

Serial communication hardware verification

The program downloaded through the in-system programming of CPLD circuit board into the supporting hardware authentication, follow these steps.

(1) determine the correspondence between pin:

Serial receive pin rxd and 12 feet R1OUT corresponding max232; serial transmit pin txd and max232 corresponding to the 11 foot T1IN; reset button S1 and the corresponding reset signal.

(2) conducted by the QUARTUS II pin assignment:

F10MHz MAXII chip in the corresponding pin number 12; S1 chip in MAXII corresponding pin number 21; rxd MAXII chip in the corresponding pin number 89; txd MAXII chip in the corresponding control pin number is 90.

(3) level defined:

Button S1 is pressed the input signal is low.

Application "serial debugging assistant" to verify the sending window, the characters need to send random input can be found by the PC, the character is sent to CPLD CPLD sent back and displayed in the receive window. Random data is sent in bulk after the analysis: the transmission 19.2kb / s transfer rate, error rate of 10-8.