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CPLD and MT8880 based remote control and sound system design

In Electronic Infomation Category: C | on April 20,2011

Abstract: CPLD and 25878-13 datasheet and MT8880 based remote control and 25878-13 price and voice communication solutions. Block diagram of the system is given and 25878-13 suppliers and the key circuit, and the key principle of the circuit are described; Finally, the key to the system host controller QUARTUS II module design and VHDL language MT8880 transceiver based on source code.

0 Introduction

DTMF transmission has a strong anti-interference ability, it can be widely used for telephone communication system, data communication system can also be used to achieve a variety of data streams and remote transmission of voice and other information.

This article describes the radio, intercom system is designed based on the principle of DTMF, the host side in the MIC with the appropriate departments through the broadcast, conference, or music player, can also be used in schools, hospitals, ships and other occasions of speaking or broadcasting.

1 System Principles

Devices used in this system are EPM7128 programmable logic device, MT8880 dual audio transceiver, MT8870 dual audio receiver. System design can be equipped with 1 to 4 host (including A, B two types of host-A large size, for desktop installation; B-type small size for outdoor installation), 5 ~ 15 1 ~ 2 sets of terminals and power . One priority of the host with 2, A-type host for the low priority, with all terminals MIC propaganda and CD / radio player; B-type hosts as a high priority, it can only MIC propaganda. When the A-type host ongoing operation, B A host can interrupt the host shouted, B operation is completed, A and then return to work status, the system block diagram shown in Figure 1.

Figure 1 System Block Diagram

2 key circuit design

2.1 host circuit

Host charged, if the machine takes light off, the unit is available keys. When available key is pressed, the machine starts, you can choose through the button MIC or CD / radio input, and then button to select the output of the appropriate department. Since then, the key operation after all the way through CPLD logic displayed in the keyboard and display panel, the other way through the dual audio power amplifier chip MT8880 sent to the TDA7496, and then by the transformer coupled output to the bus, and then the terminal mounted on the bus after decoding, that is, can generate the appropriate control and speaker output signal. Figure 2 shows the block diagram of the system host.

Figure 2 Block diagram of system host

2.2 bus converter

Speech signal generated by the host and dual audio signal by the power amplifier output to the line transformer, then the line output transformer coupled to three core bus. Core in order to reduce the number of transmission lines, an increase of the transmission line distances can be output in line after the load by Eritrea asthenosphere 24V DC power supply, this would eliminate the power line terminals. The bus conversion circuit electrical schematic diagram shown in Figure 3.

bus conversion circuit in Figure 3 Circuit Diagram

2.3 dual audio transceiver circuit

MT8880 dual audio transceiver circuit chip can be achieved.

This design uses a single-ended input. Which DTMF signal input from 2 feet input, and then decoded by the MT8880 by the D0 ~ D3 output to the CPLD, and then by the logic in the CPLD and the relationship between internal operations to generate a corresponding control operation signal. DTMF output from the CPLD, after scanning the keyboard can be used to determine the current control state, to generate the appropriate code, and then by the D0 ~ D3 output to MT8880. Where D0 ~ D3, @, RS0 and CPLD interface for the MT8880, MT8880 @ for the input clock, RS0 choose to register, D0 ~ D3 for the input and output bus. DTMF transceiver circuit of the electrical schematic diagram shown in Figure 4.

Figure 4 MT8880 transceiver circuit electrical circuit diagram

3 CPLD part of the design

DTMF transceiver system state program design process and on-site as shown in Figure 5. valid and effective, that is a keyboard trigger signal input, this time sending and receiving program starts sending DTMF input code; if Valid invalid, the DTMF transceiver state program is closed. Take control of the bus, ZY, ZY effective, the machine can not boot; ZY invalid, the machine can read and write operations on the bus. S1 for the receipt of a valid coded signal generated by the trigger signal; Pri [0] native priority bit.

CPLD programming Figure 5 Figure

Following the MT8880 transceiver is based on VHDL procedure:

4 Conclusion

Under this design can be realized based on CPLD and the MT8880 radio and intercom systems. The circuit debugging, you can complete in three core lines of high-quality audio and control signal transmission. Currently, the design has been design verified by experiment the feasibility and benefits of practical and high reference value, can be applied to hospitals, ships, mines and other related fields.

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