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Based A / D converter TLC5510 video data acquisition system

In Electronic Infomation Category: B | on April 19,2011

Video image acquisition and GTL2000DL datasheet and abroad

many ways, basically divided into two categories: automatic image acquisition and GTL2000DL price and image acquisition based on the processor. Automatic image capture more video using a special decoder chip, such as the SAA7113, TVP5150, etc., automatically modular transformation, and GTL2000DL suppliers and output line, field signal in order to achieve the memory address generation, DSP-based processor, generally, in addition to the initial acquisition mode of settings, the main processor does not participate in the acquisition process. Advantage of this method is not CPU-time acquisition, real-time is good, suitable for high precision image data and the algorithm complexity of the situation, such as lane detection, vehicle identification such as the direction of the application. But the programs on the processor speed has a high requirement, high cost, and circuit complexity. Processor-based image acquisition is synchronized with the video signal generated by the chip separation of horizontal and vertical interrupt signal, the internal microprocessor A / D converter to capture images. Image acquisition process under the control of the CPU, the CPU starts A / D conversion, convert the data obtained. The program is characterized by a simple circuit, low cost, easy to implement and can meet the needs of a simple image acquisition system. But the CPU-time data acquisition, acquisition speed by the microprocessor A / D conversion time limit.

This paper, based on independent high-speed A / D converter TLC5510 the video capture system design, to high precision high-speed video data acquisition, applicable to smart car competition, indoor guide, the team simulation platform, the mobile machine road conditions were relatively homogeneous platforms. Image processing algorithm is simple occasions.

1 System Architecture

The system applies to PAL standard analog camera output video signal acquisition. General analog camera and the operating principle is: according to a certain resolution to interlaced image sampling points on the way, when scanning to a certain point, through the image sensor chip to the point image intensity conversion into correspondence with the gray into the voltage value, then this voltage output through the end of the video signal. Meanwhile, the video signal ended output also implies a field sync signal, horizontal synchronization signals, even and odd field sync signal and other information, so the actual output is composite video signal.

MC9S12DGl28B as the processor of the system uses for the signal characteristics, the main design ideas are as follows: first, through a special chip LM1881 video sync signal separation line extracting a composite video signal sync pulses, blanking pulses and vertical sync pulses, and convert them into digital level port directly lost as a microcontroller interrupt control signal. At the same time high-speed A / D converter TLC5510 the video signal A / D conversion, the video-voltage analog signals into digital signals representative of the output image intensity. Then used as the video data FIFO memory uPD42280 cache line interrupt service function to write its control, the A / D conversion data is written to its memory. Finally, when an image at the end of the interrupt service function by the presence of 8-bit microcontroller IO port to the video data read back. In order to ensure the stability of the data, between the microcontroller and the FIFO memory, added a 74HC245, as a data buffer. To ensure the acquisition synchronization, LC5510 uPD42280 and 74HC245 crystal using the same active as the conversion clock source for reading and writing. Framework of the system shown in Figure 1.


video acquisition system block diagram in Figure 1

2 Hardware Design

A video acquisition system to collect data within the image determines the amount of image quality, it is often said that the resolution or called pixels. PAL format of the signal in accordance with the characteristics of 25 frames per second scanned image, each frame is divided into two parity, then an image of the scan time is 20 ms. Camera on the market today, whether CCD or CMOS imaging, the basic vertical resolution of 400 lines in the above. So push the duration of single video signal is less than about 20 ms/400 = 50s. So, how in the video signal within 50s fast A / D conversion, the gray value of more data to improve the lateral resolution video capture system to become a key issue.

2.1 high-speed A / D converter

TLC5510 TI produced in the United States CMOS, 8-bit high impedance parallel analog components (ADC). It uses a single +5 V power supply, can provide the maximum sampling rate of 20 MSPS. TLC-551O of the full input range is 2 V, TLC551OA the full input range is 4 V. TLC5510 uses a semi-structure and CMOS Flash technology, so the device greatly reduces the number of comparators, and high-speed conversion while maintaining low power consumption. The recommended operating conditions, TLC5510 consumes only 130 mW.

TLC5510 ADC includes clock generator, the internal reference voltage divider, a set of relatively high 4-bit sampling, encoders, latches, 2 sets of samples with low 4-bit comparators, encoder and 1 a low 4-bit latch and other circuits. TLC5510 external clock signal CLK through its internal clock generator can produce 3-way internal clock to drive the comparator group 3 samples. Reference voltage divider can be used for the 3 groups provides the reference voltage. Output A / D signals from high-high four 4-bit encoder directly, while the lower 4 bits of the sampling data from two low-4 encoder to provide alternate. TLC551O the work of the timing shown in Figure 2. Clock signal CLK falling edge of each acquisition analog input signal. N times the first data collected after 2.5 clock cycles after the delay to the internal data bus. At this point if the output enable terminal OE is valid, the data can be sent to the 8-bit data bus.


Figure 2 TLC551O work timing

TLC5510 not only has high-speed A / D conversion function, but also with internal sample and hold circuit, which greatly simplifies the design of peripheral circuits. Only need to use an internal reference resistor and reference voltage divider can be realized VDDA form 2V full-scale conversion range. Because the normal composite video signal does not exceed the maximum voltage 2V, so the design process in this system, the TLC5510s REF-BS-side shorted to REFB side, REFTS end shorted to REFT side, to obtain 2V reference voltage. ANALOGIN pin input signal from the screen, while the active use 4MHz crystal clock signal. By calculating we can see the chip in the single video signal scan time can be 200 times the A / D conversion, for the simple image algorithms, the lateral resolution is fully able to meet the requirements. If the clock frequency to improve TLC5510 work, you can continue to improve the lateral resolution. Subject the TLC5510 work in extreme cases (20 MHz sampling rate), horizontal resolution up to about 800 points, that is, more than 30 million pixels. Power, because of the TLC5510s OE pin to GND, the chip is always active low state, so the A / D conversion will continue to work. 8-bit data output directly to the next level of the input FIFO memory, the memory by the processor determine whether the A / D conversion data is written.

Specific application circuit shown in Figure 3. Note that, because the TLC5510 the AGND pin and DGND pins are not connected internally, so need to be connected externally. Inductor or ferrite bead is recommended to remove the analog to digital signal noise. Meanwhile, VDDA and AGND, VDDD and DGND pins should be respectively 0.1 F decoupling capacitor is recommended to use ceramic capacitors, and supported by more than 10 F tantalum capacitor energy storage.


Figure 3 TLC5510 Application Circuit

2.2 FIFO memory,

UPD42280 is a 2 Mbit dual-port FIFO (first in first out) memory. In this system as A / D conversion data cache, large capacity and high cost performance, to meet an image data of about 250,000 pixels storage requirements. A / D conversion clock according to certain data in order to write or read out the beat, its read and write clock rates up to 33 MHz. uPD42280 itself is 8 bit parallel data input and output, by controlling its WE pin, WRST pin, RE pins and RRST pin high and low level, the write and read data. Figure 4 uPD42280 read and write cycle timing.


Figure 4 uPD42280 read and write cycle timing Control of the write cycle

, WE is active low if the state (WRST at this time is high), data is written before the arrival of the next cycle of rising edge of the memory address; WE is high if the disabled state. Write suspended, write address pointer maintained. WE is active low in the state. If WRST is low, the write address pointer back to the address from the current address of 0, WRST back high, the data is written from the address 0. Reading the control cycle, RE if a low active state (RRST at this time is high), rising to the data in the next cycle is read; RE disabled if in a high state of suspended read, read address pointer maintained. RE is low in the active state, if the RRST is low, the read address pointer back to the address from the current address of 0, RRST back high, the data is read from the address 0.

In this system, uPD42280 read and write clock work with the TLC5510 use the same clock signal (4 MHz), both to ensure the FIFO write and A / D conversion operation of the synchronization to avoid data miss or mixed then the phenomenon, but also the data read, read speed is only read by the processor time to decide IO port. IO Port controlled by the processor to read, write enable signal, read, write address reset signal, to be completed by an image data read and write and update. The processor bus frequency 32 MHz, the single screen signal scan time (approximately 50 us), IO port into the final read about 190 effective pixel gray value. Removal of the line blanking area and the image center is in need of a point omitted, the system can capture video signals of each line to the effective pixels is 160.

Should be noted that, uPD42280 external circuit itself is very simple, just add the power and ground to a decoupling capacitor. However, due to FIFO memory is different from RAM, is not an internal address to operate, only the address of a simple reset. So be sure to pay attention to software control logic, read and write in strict accordance with the timing to control the four pins, in order to ensure the integrity of an image is written and read.

Innovation of this system lies in high-speed A / D converter TLC5510 used in conjunction with the FIFO memory uPD42280, the conversion of video signals and data storage. This makes the whole front end conversion and storage of controlled entirely by the number of IO ports on the microcontroller itself, the performance requirements of the low, low resource requirements, using only two interrupts microcontroller and multiple common IO port. This design makes the system highly portable, can be used for a variety of microcontroller or DSP. Both the core and the devices are 8 bit parallel data input and output, very fast, can achieve high-speed video data transmission.

3 Software Process

Software part includes initialization, write, read and image processing. First, the IO processor port, interrupt port initialization, PORTB8 bit as data entry, input enable; PORTK0 ~ PORTK3 as memory read and write enable and address control lines, output enable, PORTJ0, PORTJ1 response lines, respectively, market disruption, rising edge triggered.

Main function is an infinite loop and continuously detect whether the image acquisition completed, if the acquisition is completed for image processing, and then make the corresponding control output. Field The main function of the interrupt service function is to clear the line counter, write the address back to zero, as preparation for a new frame. Line interrupt service function from the main function is to increase the line counter to determine the number of rows in the current image. Collected to determine whether to initiate, control write enable, to determine whether the end of the collection, control write disabled, the control reads the address back to zero, so that can read the data through a buffer, through the 8-bit microcontroller data bus read two-dimensional array, and notify the main function of the image data is ready. Specific processes shown in Figure 5.


software flow chart in Figure 5

4 experimental data

Experimental environment model is white with black lines running track, a real image data acquisition is 160 pixels x20 line, image processing, edge detection algorithms and a mainly linear interpolation, the purpose is to get the runway centerline trajectory. Figure 6 shows the single A / D conversion data, which correspond to high values ??gray white, black and gray lines correspond to low values, the abscissa for each sampling point in the actual image in the proportion of X-axis coordinate, dimensionless is 1.


Figure 6 one-way A / D conversion data

Shown in Figure 7 for the system to identify different types of road conditions, the camera shot above is the actual image, below is the image data by the edge detection and linear interpolation processed by the center line of track. Abscissa for the center line of each row in the image in the actual proportion of X-axis coordinates of the center line of the vertical axis for each line of the actual image in the proportion of Y-axis coordinates, the dimensionless 1. The horizontal and vertical coordinates can be measured by calibration of the image by two-dimensional coordinates of the real world. Then the corresponding values ??are stored in a static two-dimensional array single chip, the control required by drawing, using look-up table; changes can also be calculated based on three-dimensional coordinates.


runway centerline Figure 7 tracks

Can be seen on the runway centerline trajectory and the actual image in good agreement. The trajectory curve can reflect the characteristics of the runway, the runway to more easily determine the type of control strategy for the next step to provide a reliable information base.

5 Conclusion

This paper, based on high-speed A / D converter TLC5510 and the FIFO memory uPD42102 video capture system for video signals ordinary single chip high-speed, high-precision acquisition provides a new idea. The system is simple circuit, stability, portability strong low processor requirements on the logo, suitable for CCD or CMOS camera most of the output composite video signal acquisition. Experiments show that the system can provide a reliable front-end image processing hardware platform.

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