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ADV7188 chip data sources offer PDF | Based PCI ExPress bus transmission of video acquisition system

In Electronic Infomation Category: A | on April 12,2011

Abstract: The PCI Express based video capture system bus transmission design. By ADV7188 video decoder that can capture analog video signals in multiple formats, but also improve the quality of the video signal; with Virtex-5 family of FPGA designs makes the system flexible, highly integrated and MC34084P datasheet and easy to upgrade. The system uses PCI Express to communicate with the PC, enabling multi-channel video capture and MC34084P price and massive data transmission over high-speed USB bus, 480 Mb / s data transfer volume increased 5 times.

Video capture system is widely used in the industrial field, with the rapid development of multimedia technology, video capture, processing and MC34084P suppliers and transmission performance requirements is also rising, such as high acquisition speed, low power consumption, interference, real time and scalability. This raises the Virtex-5 as the core, the ADV7188 video decoder is, PCIExpress set for the transfer bus consisting of video capture, compression, transmission in one of the multi-functional video processing system. The system enables real-time massive multi-channel digital video transmission. Virtex-6 supports the PCI Express 1 channel transmission rate has reached 3.2Gb / s.

As the system design, small size, low power consumption and meet the working conditions, can be used in public places, factories and underground operations, such as remote control environment to be more than the bad place.

1 PCI Express bus Introduction

PCI Express is a major serial standards, it is the third generation in 2002 came out I / O interconnect technology, PCIX from PCI to provide a upgrade path. PCI Express is the PC industry standard interconnect technology with scalable capacity, scalable, feature set, strong market adaptability and low cost characteristics. The high-speed serial standards to each channel can be 2.5 Gb / s wire-speed two-way communication, hierarchical data packet structure is conducive to modular design. Through a simple upgrade will be able to achieve more bandwidth is increased (up to 80 GB) - 1,2,4,8,16 and 32 channels. PCI Express advanced features, such as reliability, power management and hot-swappable, with a virtual channel, service level and quality of service (QoS) features such as support for the next generation of D / multimedia services.

2 Hardware Design

The system uses video decoder + FPGA, PAL, etc. Its function is to receive standard analog video signal is converted to meet the ITU-R BU. 656 format digital signal, the multi-channel video package, the PCI Express bus transfer to the computer. ADV7188 used here to collect

PAL format video signal, Videx-5 of the I2C bus controller through the I2C bus to configure and control. Use Virtex-5 series XC5-VFX30T, this device has powerful processing capability and rich external device interface, a variety of different applications to meet the control and image output needs. Virtex-5 devices with video processing IP core, can be configured according to requirements, but also has PCI Express, PPC440 and other IP core, PPC440 at 667MHz clock frequency, the digital processing capability can be achieved 1600DMI / s, with 256 KB of internal SRAM . Virtex-5 with two I2C interfaces, up to 8 (32 bit) has a master of the peripheral bus interface, support for external, internal and inter-memory DMA mode 2 10/100/100 Mb / s half-or full-duplex Ethernet interface, Figure 1 block diagram of the system hardware.

Figure 1 System hardware block diagram

3 main components of the principle to achieve

3.1 video capture processing circuit

3.1.1 Video Decoder Selection

In the choice of video decoder, the main consideration functionality, performance, size, cost and low power consumption, etc., so choose the ADV7188 video decoder device type. The device has the following features:

Can automatically detect NTSC-M/J/4.43, PAL-M/N/B/G/H/I/D and SECAM standard signal input; single clock 28.636 36 MHz; 4 analog Video Collection 12-bit AD; 5 line adaptive comb filter; reduce the digital noise; integrated adaptive peak white level of the automatic gain controller; has locked weak, and unstable video source noise design; 12 analog input channels; input video signal amplitude, is 0.5 ~ 1.5 V; in case of no input video signal can be generated on-line vertical sync signal; luminance bandwidth of edge enhancement is programmable; color, contrast, brightness, saturation, programmable; YCbCr output in the form to 20/16/10/8 bit 4:2:2; supports industry-standard I2C interface; power supply +3.3 V, 1.8 V; under the power mode; 80-pin, lead-free LQFP; operating temperature of -40 ~ +85 .

3.1.2 video capture circuit works

ADV7188 video capture circuit is that the core collection of multi-PAL, NTSC or SECAM analog video signal format, with enhanced weak analog video signals, for noise reduction and improve the function of the quality of digital video signals. AD7188 can be found in the detailed circuit ADV7188 device manual. The ADV7188 to the power requirements higher, the system is designed to isolate the power supply, decoupling, low-frequency filtering processing. In order to widely used, this uses a frequency of 28.636 36 MHz quartz crystal resonator, the frequency difference is 20 ppm. Figure 2 shows the crystal oscillator circuit video paperback.

Figure 2 paperback crystal video circuit

According to PCB layout, Cstray usually 2 ~ 3pF, ADV7188 pin to the power supply to the device capacitance Cpg to 4 pF, quartz crystal resonator load capacitance Cload to 15 pF. The C1 = C2 = 2 (Cload-Cstray)-Cpg calculate the capacitance of C1 and C2 is 24 pF, in accordance with the E12 series of preferred values, select the capacitor value of 22pF.

Next design using ADV7188 power mode, when this film is not analog video input or no work, under its power, its power will be reduced to 0.6 W when working around 1 mW, can greatly reduce system standby power consumption.

3.1.3 video capture circuit configuration

In I2C bus controller FPGA to design, configure, and video decoder for the I2C interface bus interface clock line. Power through the FPGA configuration, to the FIFO on the FPGA initialization, initialization data for the video capture circuit configuration data, configuration data in Table 1.

Table 1 configuration data

3.2 FPGA

3.2.1 FPGA device selection

FPGA choice models based on the following aspects: a PCIExpress bus; channel not less than x8; with embedded microprocessor; the appropriate I / O pin count and resources to support the required level of standards; with more low power consumption; the right price.

Therefore, the choice Xilinxs Virtex-5 family XC5VFX3-0T, package for the FF665 PCI Express bus; with PowerPC440 embedded microprocessor. Configuration chip capacity of 1 GB of optional CF card.

3.2.2 FPGA performance and resources

1) clock resources, global clock bus 32, the entire device clock control of all resources, and can drive logic signal;

2) clock management clock deskew, frequency synthesis, phase shift and dynamic reconfiguration and other functions;

3) as a broad-spectrum frequency PLL frequency synthesizer, and the DCM with the CMT as an external or internal clock with jitter filter;

4) BLOCK RAM 2 448 Kb, can be configured as RAM, dual-port RAM and FIFO and so on, and its contents can be initialized;

5) configurable logic block of combinational logic and sequential logic to achieve a major resource;

6) SelectIO resources to support a wide variety of standard interfaces. Including the output intensity and the slope of the programmable control and NC-chip impedance termination;

7) SelectIO logical resources include combined input / output, three-state output control, storage input / output, storage tri-state output control, DDR I / O and DDR output tri-state control;

8) Senior SelectIO logic resources and convert the input and output strings and string conversion;

9) DSP slices 64 550 MHz DSP48E slice, each DP48E includes a 28x18 multiplier, an adder and an accumulator. The FPGA Edit using Xilinx ISE FPGA also observed the internal structure.

3.3 data cache

The PCI Express bus baud rate is 2.5 Gbps, greater than 1 channel digital video signal after collection. When the video data within the FPGA via the parallel bus passed through the configuration for the asynchronous data input and output of the FIFO buffer, to improve bus efficiency. If the PCI Express bus 1 channel, PAL format video into a common format for 8-bit YUV 4:2:0 digital video, according to PCIExpress bus transfers valid data 1.62 Gb / s calculations, in theory, can transmit 36 ??Road.

3.4 FCI Express interface

Use of the FPGA with a PCI Express to design, selection of Xilinxs Virtex-5 LXT family of FPGA, using its PCI Express IP core within the design, complete the following functions: user interface of the local link framing interface; 64 bit data bus width and 3 remind bus; package of interfaces used to label the package with the starting frame (SOF) and end of the frame (EOF); ??transmit and receive packets interrupt the direction of the user interface features; framing error detection support; more channel configuration support: 1, 2, 4 and 8; this channel configured for 1; per channel 1.62 Gb / s or higher throughput; end module with integrated auto-negotiation function, can Some channels do not work when the design uses less bandwidth; physical layer used in 8B/10B encoding and decoding. Although the development of this program is difficult, long cycle, but with the external circuit around a simple, low cost of hardware, design flexibility, high integration, and easy to upgrade and so on. The interface circuit shown in Figure 3.

Figure 3 PCI Express interface circuit

3.5 Clock

The design requires four clock signals, including video decoding clock signal requires the highest precision of the clock must be within 50 ppm, followed by the work of PCI Express bus clock frequency. Clock signal within the FPGA DCM and PLL treatment was completed to the skew of the clock signal, phase shift and frequency synthesis functions.

3.6 Flash and DDRSDRAM

To make the design flexible, scalable and upgradeable, reserved Flash and SDRAM to store the program and run the program, to meet intelligent and easy-to-Ethernet remote control requirements.

3.7 Ethernet interface

By FPGA + PHY + transformer component Ethernet interface, you can use this interface to load the program, also used this interface and Internet connection. Using XILINX FPGA development software company ISE, through the FPGA, IP core according to TriMode Ethemet MAC.

3.8 DMA Transfer

This design uses the internal DMA mode data transfer. Digital video signals within the FPGA via the parallel bus passed through the FIFO data buffer, the DMA mode to pass through the PCI Express computers.

3.9 FPGA configuration

Virtex-5 configuration program using System ACE (System Advandced Configuration Eviroment) in the System ACE CF (CompactFlash). System ACE CF memory card with stored data, through the System ACE controller to the FPGA, the data configuration. System ACE CF with a capacity of 1 GB of CompaetFlash card, System ACE CF is pre-configured solutions, without writing any program, you can simply debugging. This solution to the old, for debugging and new versions are loaded onto the same CF card, to shorten the development cycle, ease of maintenance troubleshooting, while the application software, the instructions included with the product is saved to the CF card, etc. , CF card upgrade can be replaced, in-system programming and remote update through Intemet.

3.10 Power Supply

Board requires power supply +3.3, +2.5, +1.8 and +1.2 V total of 5. +3.3 V power supply which is external input, about 20 W; +1.8 V provided to the FPGA and the ADV7188 the secondary power supply, the other to the FPGA to provide secondary power supply. +3.3 V power supply for the power level provided to the FPGA of +2.5 V, +1.8 V and +1.2 V for the power plane split. Provided to the ADV7188 to 0.5A +1.8 V supply current in accordance with the design, the actual typically 100 mA. Decoupling capacitor and the corresponding placement of components in the same layer, reducing the impact of vias.

3.11 PCB design

PCB layout follows the signal integrity design requirements. 10 layer PCB, the first design of power and ground planes, including power supply layer 2 layer, 4 layer ground plane, symmetrical distribution. In addition to all other work outside the Ethernet adapter for a power supply to ensure the integrity of the ground plane.

The PCI Express bus to 2.5Gb / s, on the Virtex-5 pin allocation, so that the pin PCI Express in their wiring as short as possible inside. When the PCB layout around the Virtex-5 PCI Express bus interface, power connector, the actual length of the differential pair is not greater than 30 mm. PCB layout, strictly control the length difference of differential lines, to avoid the signal from the delay does not exceed the rise time, overshoot and ringing occur lead, PCB layout based on the characteristics of PCI Express signals, the definition of differential difference in length does not exceed 1 mm, the result does not exceed the actual wiring 0.2 mm. Differential impedance on the PCB (100 10) , consistent with single-ended impedance PCIExpress specification (50 10) requirements.

3.12 operating system The design of the FPGA

with PPC440 core, using real-time multitasking operating system (Vxworks), according to the actual requirements, from Vxworks kernel (wind) task management, communication mechanism, system configuration, several aspects of system interface designed to ensure system security and reliability. The design already has a mature Vxworks operating system.

3.13 FPGA debug

FPGA development, including process management and design input, simulation, synthesis, constraints, implementation, commissioning and configuration layout, in which the debugging FPGA design cycle takes about 80%. ISE with advanced components, including on-line debugging (ChipScope Pro), layout planner (PlanAhead), Timing Analyzer (Timing Analyzer), the layout planner (FloorAhead), low-level editor (FPGA Editor), and power analysis device (Xpower), and third-party software ModelSim, use the appropriate tools to effectively accelerate the design process to avoid re-design, improve design productivity, and significantly improve design performance, lower power consumption will reduce overall system cost.

4 collection, transmission and authentication

A video signal generator as shown in Figure 4 analog video signals. Through the analog video signal acquisition, the bus transfer process, the computer display shown in Figure 5 for digital video, and analog video monitors display the same image, the naked eye can not distinguish the difference, meet the requirements. A variety of standard analog video capture detection screen, showing no distortion of the normal, confirming the design of video capture and data transmission to achieve the desired results.

Figure 4 analog video screen

Figure 5 digital video screen

5 Conclusion

With multimedia in the industrial and commercial aspects of the widely used for video signal acquisition, data transmission speed, reliability, integration and put forward higher requirements. This design of PCI Express-based video capture system for collecting weak or interference in video signals, high integration, massive video data for transmission to solve the transmission bottleneck.

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