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AD9779A register allocation and optimization of PLL frequency

In Electronic Infomation Category: A | on April 12,2011

With the development of science and MAX763ACSA datasheet and technology, communication, measurement, and MAX763ACSA price and other fields of signal sources becoming more demanding, high-speed arbitrary waveform generator become a hot market. High-speed DAC, as a key part of the arbitrary waveform generator, the performance of high-speed signal has a tremendous impact. AD9779A is currently able to buy high performance, high-speed DAC chip, the internal PLL frequency integrated circuits, synchronous control, gain control function module, through the SPI interface and MAX763ACSA suppliers and external communications, you can set the optimization of various functions to achieve the best performance .

1 AD9779A Introduction

AD9779A Analog Devices is the companys dual-channel 16-bit high-speed wide dynamic range of the number of DAC, sampling rate 1Gsps, allowing up to the Nyquist frequency, multi-carrier generation. 0.18m CMOS production process, operating voltage 1.8 ~ 3.3 V, sampling rate 1 Gsps power consumption 1 W, with a high speed, low power consumption. AD9779A also includes high-performance low-noise PLL clock multiplier circuitry, can reduce the burden of board-level clock input. AD9779A can be used in wireless infrastructure (WCDMA/CDMA2000/TD/GSM), digital frequency synthesis, broadband communications and other fields.

2 AD9779A SPI-communication

2.1 AD9779A the SPI Interface Overview

SPI bus system is a synchronous serial peripheral interface, which allows MCU with a variety of serial peripheral devices to communicate, to exchange information. Through the SPI interface can be configured AD9779A internal registers, set the various functions to meet the design requirements. AD9779A The SPI interface supports single-byte or multi-byte transfer, including the format of high priority and low priority by the four lines, namely:

Serial Clock (SCLK), as the data input and output of the synchronous clock, the maximum clock rate of 40 MHz. The rising edge of input data latch clock, falling data output.

Chip Select (CSB), low start and maintain a communication cycle to the communication cycle, high, SDO and SDIO high-impedance state.

Serial data input / output (SDIO), the pin can be used as a unidirectional data input port, or as a bi-directional data input and output ports, through the registers (0x00, bit7) control, the default is one-way data input.

serial data output (SDO), as the data output port, SDIO port configured as a two-way, SDO is high impedance.

Internal configuration of any change will take effect immediately after the last written, so when there are multiple bytes can be written to the register to change the configuration of a communication cycle. Meanwhile, in order to prevent unforeseen circumstances change the configuration register is recommended to use single-byte transfer.

2.2 SPI interface operation

AD9779A of a communication cycle consists of two stages. The first stage is the instruction cycle

(written instructions to the device) and the first 8 rising edge of SCLK line. Provisions of the serial controller command byte data cycle, which is the second phase of the communication cycle is a read or write data, the number of bytes of data transmission and the first register address. Each communication cycle for the first 8 rising SCLK command byte written to the device.

Remaining SCLK is the second phase of the communication cycle. The second stage is the actual equipment and the MCU data transfer phase. 1 can be transmitted every 4 bytes, the number of bytes transferred by the instruction cycle decisions. Register in each byte is written immediately after the last change.

SPI commands are listed in Table 1.

Table 1 SPI command

, The decision is read or write operation. Logic 1 a read operation. Write logic 0.

N1 and N0 data transmission cycle determined number of bytes transferred. N1, N0 the number of bytes that are listed in Table 2.

Table 2 N1, N0, said the number of bytes

A4 ~ A0 to determine which register in the data transmission can be accessed. In the multi-byte transfer, this address is the starting byte address, and the remaining register addresses automatically generated by the device. Highest priority of the register configuration sequence shown in Figure 1.

Figure 1 highest priority register configuration sequence shown in Figure

2.3 AD9779A introduces the main register

AD9779A 32 internal registers, each register is 8 bits, each has its own specific function. AD9779A main registers listed in Table 3.

Table 3 AD9779A main register

3 AD9779A registers configuration

3.1 Hardware Design Samsung S3C2440

this paper as a control chip for the entire system. Is the ARM processor S3C2440, which includes LCD controller, SDRAM controller, 3-channel UART, audio interface, USB controller, 2-channel SPI, with its low-cost, high-performance features for various embedded fields. S3C2440 as a master device from the device to configure the hardware connection AD9779A shown in Figure 2.

Figure 2 S3C2440 and AD9779A interfaces

S3C2440A the SPI interface and external devices at the same time send / receive 8-bit data, to synchronize with a clock line. When the SPI is the host, the transmission frequency by setting the corresponding bit SPPREn register to control the maximum rate should be less than 25 MHz. If the SPI is a slave, the other host to provide the clock. Set a GPIO as nSS, when the program writes data to the SPTDATn register, if ENSCK, SPCONn register MSTR is set, SPI transmit / receive operation will also start. Bytes of data to the SPTDATn writing before, nSS should be activated.

SPI programming interface, the basic steps are as follows:

Set the baud rate clock prescaler register (SPPREn);

Set SPCONn configured SPI module; Set a GPIO pin

, as nSS, low Chip Enable;

check the data transmission to send data ready flag (REDY = 1) of the state, and then write data to the SPTDATn;

Write data 0xFF receive data to confirm REDY SPTDATn set 1, and then read the cached data;

nSS pulled, lifted chip select.

3.2 software S3C2440

main achievement of reading and writing software design features AD9779A registers, PLL frequency lock for the back to prepare. In the ARM Realview MDK environment using C language software.

4 PLL frequency band at ambient temperature optimization lock

AD9779A the PLL VCO (voltage controlled oscillator) the effective operating range of 1.0 ~ 2.0GHz, in this frequency range overlaps with the 63 shown in Figure 3. For the desired VCO output frequency, there are several valid values ??for the PLL frequency band selection. However, the locking range of each band varies with temperature. Center frequency of each band decreases with increasing temperature, the decrease with temperature increase. Each device has a specific optimal temperature PLL frequency selection value, and also between the various devices 30 ~ 40 MHz error. Therefore, the need to select the appropriate device for each frequency band PLL value.

Figure 3 25 environment typical locking range

AD9779A with PLL frequency automatic selection feature, when the auto-select feature is enabled, PLL lock to get a band, read through the SPI registers by the corresponding value of the band, that is optimal under the current temperature band. The entire temperature range in order to get the best PLL performance, PLL must be set in table 4.

Table 4 PLL settings

4.1 PLL using the temperature sensor allocation band

When the device starts at one extreme temperatures, PLL frequency automatic mode the value obtained in another temperature may not remain locked. AD9779A at -40 ~ +85 environment PLL frequency band configuration is as follows:

configuration N1 (Register 0x09, Bits [6:5]) and N2 (Register 0x09, Bits [4:3]).

Set PLL band is 63 (Register 0x08, Bits [7:2]), open the PLL Auto mode.

PLL_LOCK until PLL lock indicator pin or (Register 0x00, Bit1) becomes high. This process is about 5 ms.

read back six of the PLL frequency value (Register 0x08, Bits [7:2]).

When the PLL automatically selected to complete, according to temperature, through the (Register0x08, Bits [7:2]) to write back to reading to set the PLL frequency bands.

This process requires testing at startup or reset the temperature to achieve the optimal value of PLL frequency band. If the best band in the range of 0 to 31 (low VCO frequencies), reference Table 5.

Table 5 PLL frequency band optimization settings (frequency value 0 ~ 31)

If the optimal frequency band in the range of 32 to 62 (high VCO frequency), refer to Table 6.

Table 6 PLL frequency band optimization settings (frequency value 32 ~ 62)

4.2 Factory calibration mode is set PLL frequency band

If there is no temperature sensor, at room temperature (about 25 10 ) under the factory calibration method. Steps are as follows:

set N1 (Register 0x09, Bits [6:5]) and N2 (Register 0x09, Bits [4:3]).

Set PLL band is 63 (Register 0x08, Bits [7:2]), open the PLL Auto mode.

PLL_LOCK until PLL lock indicator pin or (Register 0x00, Bitl) becomes high. This process is about 5 ms.

read back six of the PLL frequency value (Register 0x08, Bits [7:2]).

non-volatile memory is written to the PLL frequency value. System power or reset PLL frequency band by the value loaded into the SPI Register 0x08, Bits [7:2].

4.3 PLL frequency Optimizer


AD9779A the signal generator is a key part of digital-analog conversion, the actual use, in accordance with project needs to configure the AD9779A internal registers. Upon examination 20 when the input clock is 150 MHz, N1 = 2, N2 = 4 Shi , PLL frequency value stabilized at 010010 (18), fvco the range of 1 174 ~ 1 231MHz. Input clock is 100 MHz, N1 = 4, N2 = 4 Shi , PLL frequency value stabilized at 100111 (39), fvco the range of 1 564 ~ 1 639 MHz. SPI communication program can also be used for the signal generator and the output DC offset calibration part, which simplifies system software design.

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