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A new sinusoidal signal generator design and implementation

In Electronic Infomation Category: A | on April 20,2011

Abstract: In order to accurately output sine wave amplitude modulation, frequency modulation wave, PSK, ASK and TDA8703T datasheet and other signals and TDA8703T price and to ensure that signals of high reliability, design a new type of sinusoidal signal generator. The sinusoidal signal generator with programmable logic devices CPLD and TDA8703T suppliers and MCU AT89S52 based digital frequency synthesis DDS frequency synthesis technology, combined with high-speed D / A device AD9713 allows the output frequency to maintain the 1 k ~ 10 MHz range, step to 100 Hz, and the CPLD through the use of digital control algorithm corresponding FM FM, AM AM and keying PSK, ASK digital modulation capabilities. The results show that the design of the sinusoidal signal generator output signal stability better than 10-4, in the frequency range of 50 load output sine wave voltage amplitude on the stable at 6 0.6 V, no significant waveform distortion, the overall performance of the system good.

0 Introduction

Sinusoidal signal source in the laboratory and electronic engineering design has a very important role, and the traditional sinusoidal signal source based on the actual needs of the general high cost, low-frequency output performance is not good and not easy to adjust, poor practicability . The design of this production at lower cost sinusoidal signal generator, can be used as He Ci Gong Zhen field recorder thrown in the Jili general sinusoidal signal can also be used as the modulation source of teaching demonstration.

Sinusoidal signal generator consists of two parts: the sine wave signal generator and produce AM, FM, keying signals. Sine wave signal generator using direct digital frequency synthesis DDS technology to achieve sinusoidal signal in CPLD and address lookup table scan, the D / A output sinusoidal signal can be obtained. With high frequency stability, frequency range is wide, easy to implement frequency step 100 Hz. All-digital structure, ease of integration, the output phase continuous, frequency, phase and amplitude can be programmed to achieve.

AM, FM, keying signal generation can be FM, AM-specific chips to sub-cut to achieve, but this method of frequency modulation amplitude modulation function, for a specific frequency and specific modulation, frequency offset is better, variable and the carrier frequency modulation, frequency requirements of any set of circumstances is difficult to achieve. In this paper, CPLD and Microcontroller AT89S52 adjustable frequency range can be achieved not only the sine wave signal, but also in the CPLD internal control algorithm with the corresponding figures can be easily implemented FM FM, AM AM and keying PSK, ASK digital modulation capabilities benefit improve overall system performance and operational reliability. Sinusoidal signal generation parts in a CPLD (EP1K30) is implemented, greatly simplifying the hardware circuit, easy to extensions, and to further create the conditions for achieving system integration.

1 Theoretical Analysis and Calculation

1.1 sine wave generation

Way by the Nbit DDS phase accumulator and the ROM read-only memory (sine look-up table) to form a numerical oscillator (NCO), digital to analog converter (DAC), low-pass smoothing filter (LPF) structure, Figure 1 shows the basic structure of DDS.

Figure 1, fc is the clock frequency, K is the frequency control word, N is the phase accumulator word length, M the median for the ROM address lines, L lines for the ROM data width, fo for the output frequency. Phase accumulator by the full adder and a register cascade composition. Fc of the clock frequency under the control of the input frequency control word K to accumulate, accumulate over time to produce the amount of overflow. The output of phase accumulator synthesis corresponding to the time of the phase of periodic signals, and this phase is cyclical, in the 0 ~ 2 range. Median phase accumulator N, the maximum output 2 N -1, corresponding to 2 phase, accumulating 1 to phase out a corresponding code, address look-up table method to obtain the corresponding value of the phase of the signal amplitude, after digital-analog conversion, a certain frequency to the signal can be output waveform, low pass filter on the output signal waveform smoothing, filtering noise and harmonics. After the control word K 2 N / K sub-additive, the phase accumulator overflows full amount to complete a cycle of operation, so the output frequency fo joint decision by the fc and K, which fo = fcK/2N and K N -1, be the minimum resolution of DDS up to fc / 2 N < / SPAN>. DDS phase accumulator theory by setting the number of bits N, the frequency control word K and the clock frequency fc value, can have any frequency of the output. 100Hz frequency step according to the requirements, select the number of bits for the accumulator 19, to calculate the clock frequency fc should be 52.4288 MHz. Stepping through the cumulative error correction software compensation methods, the use of the existing 52.416 0 MHz crystal completely precise requirements of Step 100 Hz.

Figure 1, the sine signal generator based on DDS schematic

1.2 analog amplitude modulation signals generated

With the modulation signal to control the high frequency oscillation amplitude, the change in its amplitude is proportional to change with the modulation signal, a process called amplitude modulation. If the carrier is uc = Uc cosct, modulated signal f (t) = cost, then the amplitude is

Common with Analog Multiplier AM Polly realized, but the external circuit complexity, the need to change the modulation to change the parameters of circuit components, cumbersome to implement. CPLD chip can be used with DDS technology and flexible digital modulation, the principle shown in Figure 2.

Amplitude modulation

Figure 2 Schematic

Waveform signal generated by the DDS as a carrier for the modulation signal in the microcontroller to the internal 1 kHz sine wave-shaped storage table, according to the tone set by the keyboard system ma (10% ~ 100%) and storage data in the table relative to CPLD and the results sent by DDS waveform obtained by multiplying, and then add the signal with the DDS to generate a corresponding coded digital amplitude waves, the D / A conversion by analog AM signal.

1.3 analog frequency modulated signals generated

In continuous wave modulation, the carrier can be expressed as uc = Uc cosct, modulated signal is U (t), frequency modulation wave is the instantaneous frequency variation and modulation signal proportional to the instantaneous angular frequency waves in addition to the carrier angular frequency c frequency, but also include a proportional part of the modulated signals and, where the proportional coefficient kf is the unit of frequency modulation caused by changes in signal strength. f (t) as the maximum of f maximum deviation, as reflected in the frequency f (t) = fc + fcos (2ft), frequency modulation wave of expression:

Figure 3 CPLD digital frequency modulation circuit, frequency control for the 5 K when the word is 50, multiplied by the cosine wave and 50, and the frequency of the microcontroller control word is passed are added into the DDS module by the D / A output frequency can be converted to wave, the design schematic shown in Figure 4.

Figure 3 CPLD digital FM schematic

Figure 4 Frequency Modulation design schematics

1.4 generates a binary PSK, ASK signal

With the digital baseband signal to control the high frequency amplitude modulation is amplitude shift keying ASK. Within the CPLD only need to set binary baseband serial number of the DDS waveform generation processing, binary baseband waveform sequence by 1, the output sequence is 0 0, the simulation waveforms shown in Figure 5.

Figure 5 Simulation waveforms binary ASK

Phase shift keying PSK is a digital baseband signal to control the carrier phase. It is the use of phase or phase change of the carrier to transmit information. PSK implementation is based on the two digital baseband signal level (or symbols) to the carrier phase in the switch between two different values, the two carrier phase is usually a difference of 180 . Waveform shown in Figure 6.

Figure 6 Simulation of binary PSK waveforms

1.5 output signal conditioning part

D / A converter circuit shown in Figure 7, the choices are 12-bit high speed D / A device AD9713, the device has better static performance and dynamic characteristics. AD9713B update rate of up to 100MS / s. As the D / A converter is for the DDS, waveform reconstruction and high-quality image signal processing applications and design, the dynamic characteristics of the chips performance particularly prominent, and has excellent harmonic suppression. AD9713 output full scale current output is determined by the VCONTROLAMP IN and RSET, and Figure 7 AD9713 using the internal reference voltage, output full scale current -20 mA.

Figure 7 D / A converter

Amplitude modulation circuit is the amplifier. High-frequency signal amplification required output voltage of the amplifier has enough conversion rate, in the case of sine wave, the amplifier to the maximum slew rate SR = 2Ц = 2Af, where is the angular frequency of the signal, A is signal amplitude, f is frequency . In addition, the amplitude modulation circuit required with a low resistance load, the amplifiers current output capacity is also an important parameter, 50 load to 6 V output signal, the amplifier must be at least 120 mA of continuous current output capability. Kaolv the above reasons, article chooses ADs High-Speed ??Op amp AD811 as the output amplifier, which is a broadband high-speed current feedback operational amplifier parameters Feichang for these indicators: small signal bandwidth (G = +2 hours) up to 120 MHz , the voltage slew rate SR is 2 500 V / s, total harmonic distortion THD is -74 dB (10 MHz), output current up to 100 mA, the short-circuit output current up to 150mA.

Amplitude modulation circuit shown in Figure 8, R3 and R4 figure diversion effect to limit for I / V conversion of current, a high-speed current feedback amplifier. It is the AD9713 output current into voltage, current through the feedback resistor Rf decision AD811 output amplitude 6 V. To increase the load capacity after the class was designed to follow after the voltage level, the last part of the analog output filter circuit, the choice of filter depends on the output waveform to the system, in the 50 load resistor voltage peak value 6 1 V.

Figure 8 amplitude modulation circuit

1.6 frequency receiver and display

Keyboard, showing some of the microcontroller used to implement user interaction. Query system uses interrupts to receive the keyboard input frequency. The frequency value on the one hand to the digital display interface to display, on the other hand into the frequency control word sent to the phase accumulation module.

2 system software design

Microcontroller program using C language environment in the Keil uV2 compile, debug emulator with WAVE6000L MAXPLUS CPLD in the under development, using VHDL language.

On the CPLD part of Phase Measurement and Digital Signal Generator by shifting the companys EP1K30TC144-3FPGA ALTERA chips have been in front of schematic analysis. Part on SCM, the program flow chart shown in Figure 9.

Figure 9 flowchart

3 function and index test

Use of test equipment: EE1641B1 type function generator / counter, DC power supply GPS-3303C, 60 MHz oscilloscope TDS1002, tester, and other high-frequency signal generator on the design of performance testing. Sine wave frequency range, step, in the 50 load output voltage range, and distortion measurements shown in Table 1, the frequency stability measurements shown in Table 2, step amplitude modulation of 10% of the test as shown in Table 3 shows, the modulation signal for the 1 kHz test frequency modulation as shown in Figure 10, binary PSK, ASK is shown in Figure 11 and Figure 12.

Table 1 Experimental observations sine wave

Table 2 sine wave frequency stability test results

Table 3 amplitude modulated sine wave test results

Figure 10 sine wave frequency modulation test results

Figure 11 ASK signal test pattern

Figure 12 PSK signal test pattern

Can be tested, the paper design of the system up to the following performance indicators:

1) sine wave output frequency range of 1 kHz ~ 10 MHz.

2) with a frequency setting function, the frequency step 100 Hz.

3) the output signal frequency stability better than 10 -4 .

4) the output voltage in the range of 50 load resistor voltage peak - peak Vopp 1 V.

5) distortion observed with an oscilloscope and no apparent distortion.

Comprehensive analysis of the indicators of test results found that the design frequency range, signal stability and high degree of distortion is good, to achieve a good performance design requirements.

4 Conclusion

To CPLD and MCU AT89S52 based on DDS technology with the sine signal generator output to ensure stability in the case of sine wave frequencies to achieve frequency is adjustable, less distortion, the frequency step is small, high precision and other characteristics, sinusoidal signal generated by the source can be widely used in teaching or general industrial and experimental situations, test results show that the proposed design of the sinusoidal signal generator is effective, easy-to-project implementation and has a certain practicality.

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