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A multi-channel synchronous data acquisition system

In Electronic Infomation Category: A | on April 18,2011

Protection or monitoring devices need multiple synchronous acquisition of voltage or current signals, are now generally way to achieve multi-channel successive approximation using ADC (such as AD7656 or ADS8-556) multi-way synchronization of data collection , high sampling rate such a program, control is simple, but requires each channel operational amplifier-based anti-aliasing filter, so to implement the high cost of large area occupied by PCB. This paper presents an analog to digital conversion using the CS5451A chip multi-channel synchronous data acquisition of the realization that this circuit is a simple way to achieve low cost. In this scenario, the processor is a Freescale MPC8313 processor chosen, frequency of 333 MHz. CS5451A If the direct control of CPU, the CS5451A chip output data rate is low, the processor speed of a serious mismatch with the ADC, CPU overhead will be greatly, this paper presents a programmable logic chip using XILINX FPGA and HCPL-2502 datasheet and the serial and HCPL-2502 price and asynchronous FIFO conversion module receive realization method of sampling data, string and HCPL-2502 suppliers and convert module only needs to receive a data to the asynchronous FIFO memory after an interrupt signal to the CPU, the interrupt service routine in the CPU read the data in the FIFO to go, this can greatly improve CPU utilization, system is simple, easy to implement.

1 CS5451A overview and circuit design Cirrus Logie

CS5451A is designed for a highly integrated analog-digital conversion chip. Integrated on a silicon wafer 6 -A / D converter, 6 digital filter and a phase with a microcontroller or DSP serial interface connection. CS5451A includes three voltage measuring channels, three current measurement channel, their main difference is that the three current measurement gain operational amplifier channels can be changed, can be set to 1 or 20 times, while a fixed voltage gain of the channel 1 times. Since -A / D converter using oversampling techniques and digital filter, so simplifying the ADC pre-class anti-aliasing filter design. In this design, the design of anti-aliasing filter is only 1 order low pass filter. CS5451A block diagram shown in Figure 1.

Figure 1 CS5451A Block Diagram CS5451A

in this design configuration is as follows:

1) ADC current channel gain of the gain is set to 1, so that the channel gain is 6 to 1, the current channels and voltage configurations, each channel is no longer differentiated, easy to make universal analog input design.

2) maximum input range is +20 V, transformer output voltage signal through the resistor divider network to generate a maximum of 800 mV voltage signal, through the ordinary low-pass filter into the ADC chip, CS5451A circuit design shown in Figure 2.

Figure 2 CS5451A Circuit Design

3) using the internal 1.2 V reference supply.

4) The clock input is 4.096 MHz.

5) data output rate of 4.0 k or 2.0 k controlled by the CPU.

2 asynchronous FIFO design

Used in this design is the XILINX FPGA chip, the companys XC3S100E, XC3S100E XILINX SPARTAN3E series is a minimum capacity of FPGA chips, this series FPGA using 90 nm technology for low-cost high-capacity demand, XC3S100E has the following resources: < / P>

1) has 2160 logic cells;

2) with the RAM resources of 87 kB (including BLOCK RAM 72 kB, distributed RAM 15 kB);

3) has two DCM;

4) with 4 multipliers;

5) can be achieved FIFO, and other IP cores.

In XILINX ISE10.1 integrated development tools, it is very easy to use XININX free IP core implements an asynchronous FIFO. Asynchronous FIFO is two independent clock domains, the data is written in a clock domain FIFO, while in another the next and from one clock domain data in the FIFO will be read out. CS5451A control system block diagram shown in Figure 3, the asynchronous FIFO and the serial and the conversion module as a bridge between the CPU and CS5451A, and converted by the serial module will output the serial ADC data into 19 parallel data (16 bit data, three of the sampling channel number from 0 to 5) to write an asynchronous FIFO, so the front of the FIFO to become the CPU of a buffer. Each completed a data receiver send an interrupt signal Pianxiang CPU to notify CPU reads the FIFO data.

Figure 3 CS5451A control system block diagram

Asynchronous FIFO IP core indicators of direct impact on the parameters of the readout speed FIFO, first of all, FIFO readout speed can reduce the CPU overhead, so that CPU can have more time to do more real-time task. Secondly, FIFO memory depth should be appropriate, the depth is too large a waste of resources, the depth is too small will cause control complex, which will take up more resources. The design of the asynchronous FIFO is the use of ISE10.1 of parameterized IP core in the XC3S100E chip implementation. CS5451A chip as a total of 6-channel ADC, ADC resolution is 16 bits, taking into account the reliability of data, the data for each ADC channel, including channel number (3 share), taking into account the CPU sometimes may not be timely go read the data, so the design parameters of the selected FIFO depth FIFO 64, the width is 19 bits.

3 FPGA-based string and conversion module design

CS5451A Master mode through a serial interface output sampling data, output data is output through the SDO, SCLK is the output serial clock, CS5451A serial output timing diagram shown in Figure 4, FSO is a frame synchronization signal that a beginning of the data, if the SE signal is high, the three signals on the effective, if low, three signals are high impedance state, in this design, CPU initialization set to high power SE level. Under normal circumstances, FSO signal is low, when there is a time to output data, FSO signal goes high, high level width is 1 SCLK cycle. The time when there is no data output, SCLK is low, FSO from high to low post, SCLK clock signal is valid, the data in the rising edge of output, SCLK cycles lasted 16x6, serial output data, MSB the first output.

Figure 4 CS5451A serial output timing diagram

The SCLK frequency is very low, the SPI controller in the use of CPU time to receive data, CPU time for receiving a 4tXINe = 1s, shown in Figure 5, a 96-bit data, receive data about a the 96s time, if an asynchronous FIFO CPU read data bus controller as fast now, if reading a byte of data needs 100 ns, take a read of data about 100 ns 12 = 1.2s ( As MPC8313 bus width is 16 bits, 19 bits of data can not be read once, so the time to read the data FIFO, the channel number is latched into a temporary register, and then read the sampling data read channel number, so read data needs to take a 12.) Only the original about 1 / 80 time and increase efficiency in the use of the CPU.

Figure 5 CS5451A a data output graph

4 interrupt service routine design

CPU sampling data is read in the interrupt service routine designed to read in the interrupt routine data taking samples and determine whether the corresponding channel number. Software flow shown in Figure 6.

software flow chart of Figure 6

5 Conclusion In this paper, CS5451A

design a common multi-channel data acquisition system, using XILINX SPARTAN3E series FPGA chip FIFO and asynchronous sampling data string and convert module design, CPU without the direct use of SPI controller receives the output of the serial format CS5451A chip data, just need to ADC serial data output module through the string and converted into the FIFO buffer, and generates an interrupt signal, the CPU read the interrupt subroutine in the sampled data. The program has been in the low-voltage relay protection has been applied to test the system through data collection accuracy can reach 0.2. Debugging found that during the PCB design, we should note the following:

1) analog circuits (differential input and reference power supply) and the digital part of the (XIN, FSO, SDO, SCLK signal) should be completely separate in different regions.

2) a good decoupling of noise generated on the inhibition of CS5451A is very important, decoupling capacitors typically 0.1 F, and into the power input pins as close as possible to achieve a good decoupling effect.

3) If the system requires work in -40 ~ +85 temperature range, requiring the sampling accuracy of 0.2, must use an external precision reference supply.

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