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A multi-channel image acquisition system software design

In Electronic Infomation Category: A | on April 12,2011

Industrial field because the environment is complex, real-time demanding, and IMP809REUR-T datasheet and often require one or more important position in the same time monitor, and IMP809REUR-T price and can switch them when needed a picture full screen. This requires a real-time video surveillance system designed both to meet the industrial field application of the special environment, with small, low power consumption, customizable features, but also able to simultaneously capture and IMP809REUR-T suppliers and multi-screen display as well with them all the way to switch.

Existing domestic surveillance program is generally used CCD camera + video decoder chip (such as SAA7113H/ADV7181B) + FPGA / CPLD + DSP implementation of the model, in which the video decoder chip CCD camera used to capture the analog signal the AD conversion, FPGA / CPLD to control the data acquisition, DSP final data processing. This method development cycles, high costs, and change is bad.

This article describes the system mainly consists of two pieces of Alteras Cyclone series EP2C8Q20818 and Philips SAA7113H video decoder chip SRAM and external memory devices and other components. Two FPGA front-end image acquisition were completed and the back-end data processing, analog video decoder chip to complete the conversion to the data signal, memory devices under the control of the FPGA to play the role of data cache.

1 System Description

System consists of acquisition module, decoding module, data format conversion module, memory module, UART modules and LCD / VGA display module, as shown in Figure 1. Four video decoder chip under the control of the FPGA1 done through the I2C-bus configuration and initialization process, output and CCIR656 compatible 8-bit YCrCb 4:2:2 format video data, including line synchronization HS, VS and vertical sync Parity field RTS0 other signals. Support the display terminal is a standard RGB format data, so the video decoder chip output YCrCb 4:2:2 format data for conversion. RGB data obtained by the conversion under the control of the FPGA2, with the corresponding timing signal, the interception to display 640x480 pixels effective, table tennis into two SRAM, and eventually in: LCD / VGA display module under the control of the data displayed on the screen. UART communication module integrated in the FPGA, the serial port through the PC, send the appropriate control commands, FPGA switch after receiving the corresponding channel of the screen.

Figure 1 System structure diagram

2 system software

System software from the acquisition module, decoding module, memory module, display module and the UART module, the software structure shown in Figure 2.

software architecture diagram in Figure 2

3 ITU656 decoding

ITU656 ITU656 standard decoding module will be based on the data stream decode 4:2:2 ITU656 standard video stream. ITU656 parallel interface in addition to transmission of YCbCr 4:2:2 video streams, there are horizontal and vertical sync control signals used. PAL standard 625 images a line scan 25 frames per second; each row of data from the 1128-byte blocks. Which, PAL standard 311 lines 23 to an even field of video data, 312 ~ 552 line is the odd field video data, the rest of the vertical control signal.

Figure 3 ITU656 data structure of each line. Each row contains the level of control signals and YCbCr video data signals. Video data word is 27 megabytes / second transfer rate, and its sequence is: Cb, Y, Cr, Y, Cb, Y, Cr, ... which, Cb, Y. Cr 3 words that refer to the same address The brightness and color difference signal sampling, the latter corresponding to the next word Y luminance sampling. 288 bytes per row for the start of the line control signal and the signal of 4 bytes for the EAV (end active video), followed by 280 fixed-fill data, and finally the signal is 4 bytes of SAV (start active video).

Figure 3 ITU656 data structure for each row

SAV and EAV signals leading 3 bytes: FF, FF, 00; the last 1 byte, said the bank is located in the XY frame position and how to distinguish between SAV, EAV. Read the rising edge of each clock coming from the decoder chip 8-bit data. When it detects the start flag FF0000XY row, the detected signals or EAV SAV signals, extracting H, F, V signal. Then a start command, and open the ranks of the counter to begin decoding the next image data, each 8-bit data in accordance with their own information, determine whether the data Y, Cr or Cb, to get Y, Cr, Cb of each component value. Decoding process shown in Figure 4.

Figure 4 decoding process

4 frame memory controller and LCD / VGA display controller design

4.1 data format conversion

Under section 2 before the introduction, from ITU656 data decoding module out of the 8-bit 4:2:2 YUV space image data, and LCD / VGA display can only receive RGB data. Because Y-CrCb4: 2:2 format can not be directly converted to RGB, so the need to convert YCrCb4: 4:4 format.

We know that the video decoder chip data by order of Cb, Y, Cr, Y, Cb, Y, Cr, ... ... of the sequence, when the store will be a Y with a C (Cb or Cr) combine to form a 16-bit data. When the data is read out when the video data must be converted to 24 bits per pixel total (Y, Cb, Cr each 8 bit) 4:4:4 data streams. 4:2:2 to 4:4:4 conversion using the simple interpolation algorithm, the sampling time, only collected once every other pixel color values ??(Cb and Cr). In the transformation, directly before a pixel color information value of Cr and Cb pixel directly assigned to the latter and Cr Cb, so you can get 4:4:4 pixel data, each pixel takes 24 bits bits wide.

4.2 frame memory controller

As an important component of the system, frame memory controller is mainly used for effective data cache. Video data under the control of the FPGA1 write two ping-pong SRAM. Ping-pong ping-pong is the key technology switching signal generation frame, the system according to the parity of the video decoder chip to generate the frame field signal RTS0 switch frame signal, which is a RTS0 cycle switch again. A cycle consists of an odd RTS0 field and an even field of composition, is a complete picture. When the frame is 1 is, FPGA final interception by the counter to display the required information in accordance with an effective pixel SRAM write timing control SRAM1, also when the frame is 0, the corresponding pixel information into SRAM2, as shown in Figure 5 Fig.

ping-pong memory diagram in Figure 5

System power, while 4 video decoder chip to work simultaneously, in order to ensure the accuracy of data acquisition and display of synchronization, the system generates a pixel clock is eight times higher than the write clock signal write_clk, so that a pixel clock cycle, the write clock signal has been eight cycles, two cycles were completed each way to write the image data process.

Because SRAM is one-dimensional storage space, an address corresponding to a data. Therefore, when writing data in the SRAM address space is divided into four segments, each segment all the way to store image data.

Application is relatively simple to achieve, to set an address register sram_addr_reg, assign it the address of SRAM control signals sram_addr. Then write the image of each road will be the starting address of the corresponding SRAM with a fixed base. Such as:


This ensures the data and the corresponding address location on the screen one relationship, in the reading program, only SRAM can be read in sequence, shown in Figure 6.

Figure 6 SRAM address verification

4.3 LCD / VGA display controller

The FPGA module is used to produce LCD / VGA display clock signal needed to CLK (pixel clock signal), VSYNC (frame sync signal), HSYNC (horizontal sync signal) and enable signal (VDEN), and The role of timing in the corresponding control, the order will display the data in the SRAM cache is read in turn, output to the LCD on the process.

LCD display timing signals required for the relationship between the main shown in Figure 7.

Figure 7 LCD timing signal diagram

In the system, LCD screen resolution of 640x480, pixel clock CLK to 25MHz, the FPGA chosen master clock 20 MHz input clock is active, then require the use of Cyclone-chip logic resources to implement the internal clock multiplier to produce the desired CLK (25 MHz), with the Verilog language of the timing generation module parameters, resulting in HSYNC (32 kHz) and VHY-NC (60 Hz) clock signal, shown in Figure 8.

Figure 8, timing verification

VGA LCD display similar principles and, in addition to the hardware is properly connected ADV7125 chip circuit, the resolution needed to generate the clock signal can be.

5 image jitter analysis and solution

Software and hardware in the system was completed when the FBI, show a picture jitter, which RTSO have ping-pong as the benchmark that all the way to switch image stabilization, the other three ways are different degrees of jitter. Which we do in-depth analysis and experimental analysis shows the structure of the entire system, the system under the control of multiple clock work together, that is, to the typical asynchronous systems. We know that the data transmitted in the asynchronous system, very strict requirements on the clock, the clock skew a little thing will bring the deviation of the effective pixels interception, and ultimately affect the image display quality.

There are two solutions, one joined the buffer mechanism, the use of FIFO data storage characteristics of data in a seamless transfer between asynchronous clock; second synchronous clock, the state machine approach makes use of asynchronous systems clock can be synchronized as much as possible. The second method used to improve the system, first of all the system frequency, frequency as the PLL comes with Quartus 6.0 generation, and use a dedicated clock pin to clock output; followed by the write clock write_clk reduced to 54M, but also is collected once every other pixel. Eventually, the four images can be stable display.

6 Conclusion

Implements a combination of paper produced CycloneII series Altera FPGA and an embedded video decoder chip ADV7181B image acquisition system. System with low power consumption, low cost, high reliability and flexibility is good. FPGA-based multi-channel image acquisition system uses two FPGA as the main chip to complete the four-way video screen display and switch the same time, realize the cascade of two FPGA configuration, the use of Verilog language of the control logic to solve the judder problem. System software is highly integrated, clear and simple hardware structure can meet the general monitoring of multiple locations where the demand for real-time monitoring, but also as a function of more complex image processing, compression, image transmission system to provide front-end data collection.

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