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A high-end audio equalization filter design and implementation

In Electronic Infomation Category: A | on April 22,2011

High-quality audio equalizer as the indispensable key subsidiary of sound conditioning in the modification of sound adjustment plays a crucial role. General audio equalizer with digital and XC901054FNR2 datasheet and analog two implementation methods, simulation methods used to achieve active and XC901054FNR2 price and passive filter, by the temperature characteristics of the device, it is difficult to achieve high reliability and XC901054FNR2 suppliers and consistency, and high cost. Digital implementation of digital filters with high flexibility and reliability. Commonly used digital filters with IIR and FIR two. IIR filter structure is simple, the required storage space, but the phase is nonlinear; FIR filter is linear phase filter, this high-quality audio processing is necessary. In this paper, the design of the FPGA-order FIR filter 1 024 digital balance filter, through the coefficient of overloading the balance to achieve a variety of frequency response characteristics.

1 a general overview

Text audio equalizer FIR filter design using polyphase filter structure, with time for space, save FPGA internal resources to achieve the greatest resources in a fixed order. Implementation block diagram shown in Figure 1.


Figure 1 Block diagram of digital filter

Input sequence and filter coefficients are stored in the cache array, the clock is synchronized by the control module generates the appropriate read and write through the address and enable signal, their output according to certain order of operations to multiply accumulate module, and output the final results. Coefficient can be overloaded by external input in order to achieve a different balance of properties. EP1C3 series FPGA M4K a total of 13 blocks, each of the 256 18 bit, take the data and coefficient bit width is 16 bits. To make full use of limited resources, and consider the audio signal processing speed and rate requirement, taking each cache memory depth of sub-module 256, will multiply and accumulate module reuse 256, 256 system clock cycles per sample point data operation, the output a filtering result. Each cache occupied a M4K block sub-module for 4 sub-modules in series, you can achieve 256 x4 = 1 024 Order of the requirements, consider the space factor, total consumption of 8 M4K blocks. It is also limited resources to achieve the highest order.

2 of each module

2.1 input sequence cache module

Input sequences using dual-port RAM buffer module module will be used 4 cascaded, as shown in Figure 2. 4 sub-blocks using the same address and write enable signal, the sampling data from the first sub-block input, the first sub-block data output to the next level sub-block is directly connected to the input, and so on. Each cache sub-block are the output data y1 ~ y4 to multiply accumulate module operation.


Figure 2, the buffer module of the input sequence diagram

The module is the key to control read and write address, write address waddr be delayed one clock cycle of read addresses raddr, so the current sub-block will be the next clock output data is written to the next sub-block of the corresponding unit. After 256 cycles, the overall data sub-block to the next sub-block.

2.2 filter coefficient memory module

Filter coefficient memory module and the input sequence corresponding to the cache module, dual-port RAM modules, a total depth of 4 dual-port RAM 256 module, shown in Figure 3.


Figure 3 filter coefficient memory module diagram

4 sub-blocks of input data using the same line, write address by decoding coefficients to generate the sub-block write enable wen1 ~ wen4 and write address h_addr, the coefficient of control input into the RAM in accordance with the order in . Coefficient read address h_addr generated by the control module, 4 sub-blocks share a read address output and data corresponding to the coefficients h1 ~ h4 multiply accumulate module, the multiply-accumulate operations.

2.3 Control Module

Generated input sequence control module to read and write cache module address, the enable signal and filter coefficient memory module, the read address and enable signals, and multiply-accumulate operations control.

Input sequence needs to shift the output cache module for operation repeatedly, each of 1 256 the number of input clock cycles, the write address input sequence must be delayed one clock cycle of read addresses in order to ensure data continuity, not lost. This newly written data is not a fixed location, the address is not required to read a simple additive relationship. To each RAM block is equal to 4 as an example of the depth of the relationship between reading and writing the address shown in Figure 4.


Figure 4, the depth of each block RAM read and write the order 4

Can see the address at this time in order to read the input sequence shown in Figure 5.


Figure 5, the depth of each RAM block 4 read address By analogy

the actual input sequence can be read address of the cache module shown in Figure 6.


Figure 6, the read address input sequence cache module

Achieve the control module shown in Figure 7. The overall count of the main counter, each clock cycle 256, address generation module took the overall count of the counter by 1, the input sequence as the read address raddr output, as shown in Figure 6 implements the address order. Read the address by the write address waddr raddr obtained by the delay of one clock cycle. Since the input sequence is output in chronological order, so the filter coefficients as long as the storage array from a corresponding sequence of output can, and counts the main counter filter coefficients directly leads to the array as the read address h_addr.


Figure 7, the control module to achieve

Main counter output after decoding circuit, the output data of the low-speed sampling clock sa_clk, used to synchronize the input sequence. Write the output of the input sequence also enabled wren, so every 256 clock cycles to time, write a data.

2.4 multiply accumulate module

Multiply accumulate module is responsible for the input data and coefficients multiply-accumulate operations per clock cycle 256 outputs a filtered result. The implementation block diagram shown in Figure 8.


Figure 8 multiply accumulate module diagram

Input sequence the output data buffer module and the filter coefficients y1 ~ y4 storage array output coefficients h1 ~ h4 corresponding module in the multiply-accumulate operations. Every 256 clock cycles to calculate a complete data sampling points 4 parts y1 ~ y4, the latch is latched, the two-stage pipelined adder final filtering results obtained by y, then the accumulator is cleared, began to prepare the next sample point data calculation. Among them, the latch and the latch clock multiplier accumulator clear signal by the input sequence after the write enable wren obtained after the corresponding delay.

3 simulation results

Balanced filter design synthesis compiler, compile the report shown in Figure 9.


Figure 9 compile reports This indicates that the 1024 order

FIR equalization filter can be achieved within EP1C3 series FPGA, only about 70% with its logic resources and about 50% of storage space. In order to verify the design functions, the filter coefficients used to initialize the memory initialization files, storage coefficient shown in Figure 10.


initialize filter coefficients of Figure 10

For visual verification, the input sequence x is taken as sequence, that is, only one data x 1, the other is 0. According to the knowledge filter and convolution, the output y = x * h = * h = h, is the filter coefficients. The simulation results shown in Figure 11.


Figure 11 filter simulation results

Input sequence x is only a sampling clock cycle for data 1, the other are all 0, fout the output of the filter results. -1 ~ -16 Visible results of duplicate data are shown in Figure 10, the same filter coefficients, the filter is working.

4 Conclusion

EP1C3 about 70% by the logic unit and about 50% of storage space, the design of the 1024 order FIR digital filter, and through the overload coefficient, can be balanced to achieve a variety of frequency response characteristics, to achieve the simple digital equalization filter The function of, to the design goal.

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