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DDS-based wireless data transmission system design and implementation

In Electronic Infomation Category: D | on March 18,2011

DDS technology is developing rapidly in recent years, the frequency synthesis technology, which uses all-digital technology, high integration, small size and MC10131L datasheet and relatively wide bandwidth, high frequency resolution, frequency hopping time is short, phase continuity is good, for broadband quadrature output, plus the advantages of modulation, and MC10131L price and constitute a convenient and MC10131L suppliers and intelligent controller interface frequency source. The reference clock frequency generally fixed, so the number of bits determines the phase accumulator frequency resolution, the more bits, the higher the resolution. DDS-based advantages, the system uses DDS technology to achieve digital modulation capabilities, give full play to the advantages of DDS, the system is simple and powerful.

1 hardware and the operating principle

This system is a wireless data transmission system, the hardware circuit is divided into the transmitter circuit and receiver circuit in two parts.

1.1 transmitter circuit

Shown in Figure 1, the transmitter hardware circuit by the controller, the modulation circuit, high frequency power amplifier, antenna, display circuit and power components.

transmitter components in Figure 1 Figure

Controller TIs high performance mixed-signal processor MSP430F169 as the core to complete the DDS, keyboard, LCD display control and information processing functions. MSP430F169 is a 16 bit RISC ultra-low-power mixed-signal processor (Mixed Signal Processor), with 1.8 V ~ 3.6 V supply voltage, the conditions in the 1 MHz clock is running, the chips current 200 A ~ 400 A, the minimum clock-power shutdown mode is only 0.2 A, in the 8 MHz crystal driven instruction cycle is 125 ns.

And has a wealth of on-chip MSP430F169 peripheral modules such as watchdog, analog comparators, timers, serial ports, hardware multiplier and so on. In this system, MSP430F169 work in the 3.3 V voltage, 8 MHz clock frequency.

Modulation circuit chip ADI AD9854 DDS chip companies as the core. The maximum system clock chip 300 MHz, the theoretical output signal frequency range is DC to 150 MHz, the highest rate of parallel programming, 100 MHz, with 3.3 V single power supply, and the controller chip matching, without additional level shifting circuit, controller and the modulator in order to achieve a seamless interface.

AD9854 supports 10 MHz and 100 MHz serial communication parallel communication mode, the system uses the serial data input. AD9854 built-in 4 to 20 multiplier PLL, an external lower frequency reference clock frequency can be obtained through the 300 MHz system clock, thus avoiding the difficulty of designing high-frequency reference clock, reducing the clock frequency interference. AD9854 reference clock input with single-ended input and differential input in two ways, to make a simple circuit, the design uses a single-ended input mode. Active external 20 MHz crystal oscillator output frequency by the PLL circuit 15 to 300 MHz was used as the system clock.

Filter used by the three inductors and seven capacitors composed of seven-order elliptic filter, because the AD9854 has a maximum operating frequency of 300 MHz, the DDS output frequency of the system the maximum operating frequency of 40%, so this program filter cutoff frequency is designed to 120 MHz, effectively filter out high frequency interference, the output signal is more smooth.

High-frequency power amplifier operating in C mode, can achieve higher efficiency. Monitor uses LCM128 128 64 dot character dot matrix liquid crystal displays, used to complete the interactive interface and information display. LM2576-3.3 power supply with three-terminal regulator chip, to provide maximum current output of 3 A, to fully meet the requirements of the system. AD9854 also work to prevent disruption of power supply, the circuit design uses a large number of filter capacitor, and digital and analog power supply were very good isolation, to prevent the digital power supply for analog crosstalk.

1.2 receiver circuit

Receiver hardware circuit by the demodulation circuit, data processor, display circuit and power components, the receiver block diagram shown in Figure 2.

composition diagrams of Figure 2 Receiver

Dedicated FSK demodulator to demodulate the core SA639DH Philips core components. It has high sensitivity, dynamic range, transfer rate, and stability is good. The signal received by the antenna input circuit out of 2FSK signal and LO signal into the multiplier for mixing the same time, and then filtered through a high frequency band pass filter to whichever frequency down-conversion, IF amplification and then The two band-pass filter into the limiting amplifier for limiting amplifier. Limiting amplified signal is divided into two, all the way directly into the multiplier, another passing phase 90 phase shift network of FM waves generated PM sending multiplier, two signals for phase comparison, the multiplier output signal by low-pass filter out of the original modulating signal, and then the signal into the comparator for shaping evacuation signal processors.

Receiver data processor also uses MSP430F169, monitor and transmitter with the same LCM12864. Compared with the transmitter, the receiver part of the low power consumption, so the receiver power supply with two 5 battery power supply in series.

2 system software to achieve

2.1 transmitter software

Transmitter power, first initialize the system, including the controller itself, the port configuration, the configuration of on-chip peripherals and external AD9854 [6], PS2 keyboard and monitor other parts of the initialization. After initializing the system into sleep mode until an interrupt generated by an external keyboard wake-up. Then get the key key code dealt with accordingly. In order to generate 2FSK AD9854 signal, the initialization process to be as follows: S / PSELECT set 1 or set to 0 to determine the input data in parallel or serial. 1 parallel, serial 0; The system uses a serial interface, under the control of the SCLK signal from the parallel input port D0 ~ D1 48 bit parallel register is written, or under the control of the SCLK SDATA written from the serial input 48 bit serial register. Transmitter of the software flow chart shown in Figure 3 (Note: In the transmitter there are three pictures of internal storage.)

transmitter flow chart in Figure 3

2.2 Receiver software design

Receivers do not need to distinguish between the character received is the English or Chinese characters, so the software design of the transmitter is relatively easier. Similarly, the start signal to initialize the processor and peripherals, to work in the waiting state of receiving information at this time, only part of the receiver RF circuit, other components in sleep mode. When the receiver is checked to have the information arrives, through the wake-up interrupt controller, the controller and then wake up the other peripherals for data reception and processing. The information received by the signal processor to determine if the characters (including English characters and Chinese characters), then enter the character LCD control mode, the character display; if a picture, the LCD into the picture control mode, the picture display. Receiver software flow shown in Figure 4.

receiver flow chart in Figure 4

3 system test results

(1) the carrier center frequency: 2FSK mode transmitter, 1 and 0 respectively corresponding to the two frequency fH = 30.003 000 MHz and fL = 29.997 000 MHz, the system is idle firing frequency of 30.000 000 MHz Therefore, select the frequency of 30.000 000 MHz center frequency.

(2) Frequency stability: the premise of the microcontroller reset, with the frequency meter test once every 2 min AD9854s output frequency, were measured 5 times, as shown in Table 1. Calculated according to test results:

Table 1 AD9854 output frequency measurements

Frequency stability = maximum frequency deviation / center frequency = (30.000 068-29.999 981) 30.000 024 = 0.000 087 30.000 024 = 2.9 10-6 (3) Transmitting power: the end of the transmit power level received 50 dummy load, with 100 MHz digital oscilloscope emission signals measured peak output voltage VP-P, according to the formula P = V2P-P/8RL, get fired power value, experimentally measured VP-P = 2.98 V, P = V2P- P/8RL = 22.2 mW.

(4) Transfer rate: transmitters, receivers in the communication distance of 10 m cases, respectively, 1.2 kb / s, 9.6 kb / s, 57.6 kb / s, 115.2 kb / s transmission baud rate 5 20 Chinese characters, Chinese characters error rate is zero.

(5) graphic transfer function: transmitters, receivers. Call the machine comes with the transmitter three graphics (respectively cock, hare, and NPU badge) to the form of lattice transmission, the receiver can be received without distortion, indicating that the system transfer function matrix with graphics.

The system simple and efficient wireless data transmission, wireless communications is a simple and feasible design. After system testing, system specifications satisfying, reliable work. In addition, because the system uses DDS to implement the signal modulation, it is relatively easy to change the modulation signal frequency, for the realization of frequency hopping communication more convenient.

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