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An improved method of TDMA implementation

In Electronic Infomation Category: A | on March 18,2011

With modern communication technology, various multiple access technology applications in daily life is becoming increasingly widespread. The so-called multiple access technology, is the number of users to simultaneously use the same spectrum, using different processing techniques, so that mutual interference between signals of different users to be received and MPC106ARX66CG datasheet and demodulated respectively. Frequency division multiple access technology is divided into multiple access (FDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDM-A). Frequency division multiple access based on a different frequency channel for communication, code division multiple access is a different code sequences to achieve communication, and MPC106ARX66CG price and time division multiple access based on different time slots for communication, it is a shared transmission medium or network access technology.

Time division multiple access technology to split into cyclical time frames, each frame is divided into several time slots and MPC106ARX66CG suppliers and then, through the media or the network to send signals. Timing and synchronization to meet the conditions, the receiver can receive at each time slot to the corresponding mixed signals without interference. Time Division Multiple Access technology with high confidentiality, large transmission capacity and other characteristics.

Present, multi-FPGA signals using time division multiple access frame format for transmission of many methods, but most methods are by using the gate FPGA chips constitute a large number of registers to implement time division multiple access. This class method will take a lot of FIGA resources, leading to the function of single FPGA to achieve greatly reduced, increased project costs, and even fewer resources for a number of FPGA chips, such methods can not achieve time division multiple access transmission. This paper presents a method based on IP core to implement time division multiple access, the use of on-chip Block SelectRAMResource (BRAM) to store data, saving a lot of logic gate resources to enable single FPGA chip can do more logic functions.

1 Theoretical Analysis

1.1 IP core

IP Core (Intellectual Property core) is a function of a specific circuit hardware description language program, the program has nothing to do with the process of integrated circuits, can be transferred to a different basis of semiconductor technology to produce circuit chip. Electronic systems using IP core design, ease of reference, modify the function of basic components is easy. IP core module behavior (Behavior), structural (Str-ucture) and physical (Physical) 3 Ji different levels of design, describe the functional behavior of the corresponding divided into three categories, namely, soft core, to complete a structural description of the solid nucleus and based on After process validation are described and the hard core.

1.2 BRAM (Block SeleetRAM Resource)

FPGA resources within the more complex types, including the following components: input / output module (Input / Output Blocks, IOB), configurable logic elements (Configur-able Logic Blocks, CLB), Block SelectRAM, multiplication , digital clock management (DCM), routing resources (Routing Resources) and so on. The proposed algorithm is the use of the integrated Block SelectRAM chip time division multiple access methods to achieve the transmission, thus saving a large number of CLB. For single FPGA to complete more.

FPGA chip BRAM each piece is an integrated dual-port physical random access memory (dual port RAM), it has two completely separate data lines, address lines and control lines to read and write, and allow two independent The system also carried out the random access memory, that is shared multi-port memory. Dual-port RAM

biggest feature is the storage of data sharing. A memory with two separate address, data and control lines, two independent controllers allows both asynchronous access storage unit. Because data sharing, there must be access to the arbitration control. Internal arbitration logic control provides the following features: access to the same address timing control unit; memory cell block access to distribution; signaling exchange logic.

BRAM work similar to the register of the work, control signals, address signals and the input and output data signals must be established at the time of the clock edge to maintain effective, BRAM clock cycle in the read and write or write to the output into the data. Divided into three kinds of read and write methods, namely the address to read and write, read-only, write-only.

1.3 Algorithm

Step 1, for example, dual-port RAM of the IP core, the programs input and output and dual-port RAM to map input and output.

Step 2, through the first set of dual-port RAM port input signal stored in RAM, through the second set of dual-port RAM to the RAM port will be stored in the data read-out.

Of 4 signals, for example, assume that each input signal sampling rate is 48 kHz, sample median is 64 bit, then each bit clock input signal is 3.072 MHz, in the first cycle, 48 kHz sampling When taken to the 3.072 MHz bit clock falling edge, it will enter an address incremented by 1. Bit in the next rising edge of the clock, according to the case of the dual-port RAM of the IP core, 4 input data will be stored into the dual port RAM input address corresponding to the current memory address, waiting to be retrieved. Since there are 4-way signal that the input signal width of 4, the dual-port RAM to store the data in the width should be 4 bits, where each address data stored in the first corresponding to the first input signal, The second corresponds to the second input signal, and so on. Dual-port RAM needed at this time the size of bit 64x4 bit.

48 kHz for the next cycle, and the front is similar to the 4-bit wide input data to a dual-port RAM to store the new 64 4-bit storage space, while the last should be stored in the 48 kHz cycle 64 4-bit data before read out, and prepared to the format of TDMA transmission out.

Step 3, read out from the second data port TDMA frame format for transmission out.

4 input signals in order to transmit time division multiple access format, the time period should be 48 kHz is divided into four time periods, each time in the division cycle, dual-port RAM to read it again to store the data. First of all, should be the first time in the division cycle 64 to read out the first 4-bit data sent to the output of time division multiple access, and then return to the starting address, the second time in the division cycle of re- 64 read out a 4-bit data, the data sent to the second output of TDMA, and so on, until all the output data 4. As in a repeating cycle of 48 kHz dual-port RAM read the data four times, so in this case the bit clock frequency will be increased to 4 times the original, so read the bit clock frequency should be 12.288 MHz.

A 48 kHz in the next cycle, after the dual-port RAM in the storage space 64 within the 4-bit data and sending out the same way as above, while four of the former 64 of data storage space has been sent, no longer need to save, the new input data can be stored in the first 64 4-bit storage space, and so on, the first 64 after the 4-bit memory space and alternate storage space 64 to store input data and alternately sent to the stored data.

It can be seen, the need for dual-port RAM size should be 2x64 4bit, the data is written in the A port, B port in the data read out.

2 FPGA implementation

The FPGA used in the experiments is the company XILINX SPARTAN 3E series XC3SS00E chip, the chip package is PQ208, the chip rate of -5, the programming language used is VHDL, Xilinx synthesis tool for the companys ISE 10.1, simulation tool is used in ModelSim se 6.2.

Correspond with the theoretical algorithm, hardware implementation of the VHDL program includes the following modules.


Use of on-chip dual-port RAM of the IP core, through the case of IP cores, using a dual-port RAM with two read and write addresses, the programs input-output and dual-port RAM to map input and output, the internal circuitry the programs input and output connected to the dual port RAM on the input and output. Input and output pins on the programs operation is equivalent to the dual-port RAM to operate. Figure 1 is a dual-port RAM, Xilinx ISE VHDL code in the integrated circuit after the register transfer level.


Figure 1 dual-port RAM, register transfer level circuits


In Port A on each falling edge of input clock clk3072, port A input address AddrIn are incremented by 1, then the rising edge of the elk3072, according to cases of the dual-port RAM of the IP core, port A of the four input data stored into the appropriate address space.




In the port B input clock elk12288 each falling edge of the port B input address AddrOut are incremented by 1, then the rising edge of the elk12288, according to cases of the dual-port RAM of the IP core, the corresponding data in the address space was read out by Dout.


Turn the output data to TDMA frame format for transmission out.

3 simulation results

The program with the ModelSim se 6.2b simulation, in the 48 kHz clock cycle, an input source to the first 64-bit input signal is 0x1111111111111111, 2-input 64-bit input signal source is 0x2222222222222222, No. 3 64-bit input source input signal is 0x3333333333333333, 4 input 64-bit input signal source for the 0x4444444444 444444. The simulation results shown in Figure 2.


Figure 2 The simulation results

Can be seen from the simulation, in a 48 kHz clock cycle, TDMA_OUT, real-time division multiple access frame format of the output is 0x11111111111111112222222222222222333333 33333333334444444444444444, that is, each frame is divided into four time slots, 4 input signal each frame transmission time slots occupied by each, through the simulation results, the availability of the method.

The VHDL language program through ISE10.1 synthesis, placement and routing, through JTAG download cable to the XC3S500E tests carried out on the board, has once again proven that the method is correct.

Integrated by ISE, you can see the process of chip resources occupied by the table below.

Table 1 chip resources


Data from the table can be seen, by using a BRAM thus saving a lot of resources, FPGA chip resources occupy an important indicator of Slices only 15, LUTs in just 29 shows, occupied by the method minimal FPGA resources to achieve the design goal.

4 Conclusion

In this paper, FPGA implementation of an improved time division multiple access methods, by using the FPGA on-chip dual-port RAM, use of IP cores, to achieve a multi-channel signal into a TDMA frame format signal for transmission, according to share resources, statistical data, we can see the same function under the premise of this method compared to existing methods, can really save a lot of chip FPGA logic resources, so that the single FPGA logic can accomplish more . However, this method will occupy part of the dual-port RAM, dual-port RAM resources in times of stress is not too applicable.

FPGA using ModelSim SE 6.2b of the simulation program, and will download to the board, verified, confirmed the availability of the method.

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