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A low-power LDO Linear Regulator wideband circuit design

In Electronic Infomation Category: A | on July 29,2011

Abstract: Design a process to achieve with HHNEC 0.35mBCD LDO linear regulator, the LDO is a low power, wide bandwidth low dropout linear regulator. Its structure and working principle of analysis and discussion of the key circuit design, simulation results verify the correctness of the design.

1 Introduction

with the scale of the development of integrated circuits, electronic equipment, size, weight and power consumption smaller, which is the power of integrated circuits, miniaturization and power management features made more high demand. With the System on Chip (SOC) of the continuous development of monolithic integrated LDO linear regulator applications are increasingly being used [1]. For on-chip LDO, the most worried about is instability caused by excessive parasitic capacitance, paper applications for the chip design of this LDO, to ensure levels of parasitic capacitance in uF can be within the scope of work, after all, another large parasitic capacitance that does not is F level. LDO linear regulator power dissipation is an important indicator of the general LDO power in tens of A or more, for example, [2] in the circuit quiescent current of 38A, [3] in the static power of up to 65A , and this is about 10A quiescent power consumption to achieve not only low power consumption, this second level of the current relationship between the resistance provided by a small gain stage, and to increase the bandwidth of the LDO.

2 LDO circuit theory and design of key modules

2.1 Basic circuit works

Figure 1 is a LDO linear regulator block diagram contains the following components: voltage reference (Vref), error amplifier, inverting amplifier, the feedback resistor network, adjust the tubes. One reference output reference voltage Vref, require it to high precision, drift small. Error amplifier output voltage fed back to compare with the reference voltage Vref, and amplify the difference between the after-phase control to adjust the power amplifier to control the state, and thus the output stable. Here C1 is the feedforward capacitor can improve the load regulation, and the addition of a left-zero compensation, Cff a zero compensation. The first amplifier is a differential pair, and most of the structure of the error amplifier, the second level for the non-inverting gain stage, the current relationship between the resistance provided by a small gain stage, and control bandwidth. Relative to the normal structure, and if driven directly by the op amp power tubes, that bandwidth is the parasitic capacitance and power tube amplifier output impedance and gain the decision, while the structure of the gain and output impedance, small compared to the op amp a lot of bandwidth naturally improve a lot. Table 1 The main design parameters for the LDO and performance indicators.

Figure 1 LDO linear regulator schematic

Table 1 LDO design parameters and performance indicators

2.2 circuit and design

(1) regulator design: MOS linear regulator voltage regulator is driven, the device can greatly reduce the quiescent current, and the smaller on-resistance makes the dropout voltage is relatively low, thereby increasing the power conversion efficiency [4]. Adjust the rate according to the square tube design specifications relationship and Vdropout 200mV, you can calculate the adjustment tube width to length ratio, combined with the transistors gate parasitic capacitance and process requirements, to consider adjustments in the case of heavy pipe to be operating in the linear area, will adjust the width to length tube is designed to: W = 6000m, L = 0. 5m.

(2) resistors R1 and R2 options: output voltage determined by the feedback network, according to VOUT = VREF [(R1 + R2) / R1], when the selected VREF = 1.25V, R1 = 625K , then R2 = 625K.

2.3 error amplifier (EA) design of

error amplifier circuit diagram shown in Figure 2. Part of the EA Power (3A) and a low offset voltage requirements, according to 2 (V T ) = A 2 VT / WL + S 2 VT D 2 and the relationship between the MOS square-tube [5], designed to control the size of each MOS, M1 and M2 of width to length ratio of 41 / 2 , M3 and M4 of the width to length ratio of 4 / 1, M5 and M6 of the width to length ratio of 2 / 1, here we take W1 = W2 = 82m, L1 = L2 = 4m; W3 = W4 = 12m, L3 = L4 = 3m; W5 = W6 = 8m, L5 = L6 = 4m. In fact, this part of the EA to make this a Ger is not less than 10dB gain and to ensure adequate phase margin, the feedback capacitor C FF is designed to 20.8pF, the C1 is designed to 1.5pF . The part of the simulation results shown in Figure 3. The results show that the design to ensure the stability of the Ger of 11dB [6].

Figure 2 EA and feedback network

Figure 3 EA of the loop gain

2.4-inverting amplifier design

-inverting amplifier circuit shown in Figure 4. This is a main loop is to obtain the maximum gain Gnon-inv = 25dB ~ 30dB.

4-inverting amplifier structure

to ensure low power consumption under the premise of I1 is set 5A, I2 is set 3A, in a small bias current and larger load conditions in order to ensure to get not less than 25dB of gain, the RF design of 500K. As with the phase gain of the amplifier decreases as the load increases, the design requires an appropriate increase in the bias current I1 and increase the value of RF [7]. The bandwidth of the transconductance of M2 by the tube and adjust W / L of the impact of the need to increase M2, W / L and the bias current I2. Figure M1 width to length ratio of 4 / 1, here take W1 = 30m, L1 = 3m, M2 width to length ratio of 110 / 1, take W2 = 110m, L2 = 1m. The simulation results shown in Figure 5.

Figure 5 with the relative gain of the amplifier

3 LDO overall simulation results and discussion

On the basis of HHNEC 0.35um BCD process, the use of cadence and Hspice circuit simulation software to do the whole simulation, shown in Figure 6 for the LDO loop stability of the simulation curve.

(a) load current of 50mA simulation curve

(b) load current is zero simulation curve

Figure 6 LDO loop stability of the simulation curve

(a) The picture shows the load current of 50mA when, LDO loop gain of 50dB, unity gain bandwidth of 470KHZ, phase margin of 74degree. (B) The picture shows the load current is zero, LDO loop gain of 63dB, unity gain bandwidth of 1KHZ, phase margin of 87degree. Figure 7 shows the LDO linear regulation curve, the simulation conditions for the C L = 1F, can be seen from the simulation curve of the LDO linear regulation of:

Figure 7 CL = 1F linear regulation curve

Figure 8 shows the load regulation of the LDO curve, the simulation conditions for the CL = 1F, can be seen from the simulation curve to adjust the load of LDO was:

Figure 8 CL = 1F load regulation curve

Figure 9 shows the LDO power supply rejection ratio of the simulation curve, the simulation conditions for IL = 1mA. As can be seen from the curve, the LDOs PSRR at 1KHZ when - 60dB.

Figure 9 PSRR simulation curve

4 Conclusion

this paper, this LDO linear regulator can ensure that the level of parasitic capacitance F range can work.

the LDO quiescent current as low as 10A, the text relative to the amplifier with the introduction of increased bandwidth of the LDO. From the simulation results can be seen in the load current Iload = 50mA, the bandwidth of 470KHz.

LDO other aspects of the indicators are to meet the design requirements.


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Panxi Wu, now the Hubei University Microelectronics and Solid Electronics Masters students, the main research direction is the analog CMOS integrated circuit design.

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