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Position:IcFull.com » IC Electronic information » Category: 8

IC Electronic information

8086 CPU-based single-chip design of computer systems

In Electronic Infomation Category: 8 | on December 24,2010

1 Introduction

With the development of VLSI technology, a chip in the millions or billions of transistors has become a reality. Today, chip makers are in the smallest, functional maximization as their own direction of development theory and MC145403DW datasheet and deep submicron effects of nuclear technology, more and MC145403DW price and more IP theory and MC145403DW suppliers and industry wide attention, the system chip is the development trend of current technology . Development of the computer through a vacuum tube computer, the computer transistors, integrated circuits, computers and large-scale integrated circuit computer, and its development has been more and more features will be integrated in smaller and smaller space. Can be expected in certain areas, the semiconductor manufacturing industry toward integrated single-chip system, the overall trend will become increasingly apparent.

the so-called single-chip computer that is a traditional PC chassis, the motherboard chipset, CPU, memory, graphics cards, sound cards and network cards to maximize the integrated in a single chip. Single-chip computer, compared with the traditional PC, weight, volume and power consumption dropped significantly, so system performance will be greatly improved, while bringing down the price of a breakthrough, directly contributed to the rapid popularization of computers.

This single-chip computer system to build standards-based 8086 CPU, integrated AMBA bus, SDRAM, 8255, ROM and other external IP, and the Altera DE2 FPGA development board to achieve the functional demonstration.

2 The Development of single-chip computer,

is a complete single-chip computer, computer system, CPU, memory, and input and output interfaces, by bus, constitute the basic single-chip computer system. Single-chip computer system-level design is carried out as the core CPU I / O and peripheral integration process, is a basic SoC design flow.

recent years, Intel, AMD and VIA and other manufacturers have introduced the microprocessor platform strategy, the microprocessor and chipset will be combined to form a complete solution, and plans to further introduce the future All single-chip integrated microprocessor chip. Frequency implementation platform strategy Intel Corporation, plans to further introduce the single-chip integration of all computer chips, but also * a 500 engineers by the R & D team, the development of its single-chip computer products, hoping to present the computer chip on the motherboard 32 fully integrated into a single chip. In the AMD Opteron processor, four separate CPU core integrated into a single silicon chip, each core has a separate 64KB data cache, 64KB instruction cache and a 512KB secondary cache, four cores shared 2MB (or more) of the three cache. So that each CPU core can give full play to their performance, and thus greatly enhance the overall processor performance.

the design of single-chip computer, is based on a model of a CPU and its peripheral I / O interface, the SoC design process. Therefore, choosing what type of CPU design has become the most important issue. The difficulty of comprehensive design, engineering progress of project, taking into account the representativeness of the selected CPU to have a certain, so the final selection criteria, Intel 8086 CPU. 8086 single chip computer based on the basic structure shown in Figure 1.



3 single-chip computer system design

8086 CPU chip has two modes, the minimum mode and maximum mode. The so-called minimal model, is only one 8086 microprocessor system, in this case, all the bus control signals are generated directly from the 8086 CPU, the system bus control logic circuit is reduced to a minimum size of the model for small computer application systems.

the present study, the minimum work model 8086 single-chip computer design. The so-called single-chip computer system design, that is, in addition to including CPU, ROM, RAM, bus, address latch, data transceiver, other than the peripheral address decoding circuitry, integrated one or more of the peripheral I / O interfaces to form a complete system. Build the system structure is shown in 2.


We design single-chip computer system 8086 to comply with AMBA protocol integrated bus, 8255 General parallel interface, and SDRAM controller. Here, the 8255 general-purpose parallel interface, as an example, the application circuit includes 8255 single-chip computer system design. 8255 as a peripheral I / O devices through the AHB bus to communicate with the 8086CPU.

single-chip computer system is an RTL-level design of SoC design process. Including the CPU subsystem design, the choice of bus and interface design, interface design, and memory unit.

3.1 CPU subsystems

CPU subsystem includes the 8086 CPU, data transceiver controller, the address latch and memory decoding circuit.

CPU and memory (or I / O ports) to exchange, CPU first sends the address signal, and then send control signals and transfer data. So need to add the address latch, the first latch address, so that the address in the read-write bus cycle stability.

data transceiver controller is equivalent to a bus switch, used to control the CPUs data bus selected from the storage unit, or I / O port to send or receive data, match the communication timing.

memory decoding circuit with the 74LS138 same principle, using the address line of ROM and RAM unit generates chip select signals. CPU power-on reset address FFFF0H, first read out from the ROM program, which is an unconditional branch, enabling the CPU to jump to the address RAM. CPU and then read out from SDRAM procedures.

3.2 bus selection and design

bus on the narrow area of chip integration and reduce bus fan-out are very positive. Standard 8086CPU, generally using a traditional three-bus structure, that is, the address bus, data bus, control bus, the bus-based architecture can be extended 8255, monitor, keyboard / mouse, network card and the like IP.

3.2.1 bus protocol choice

the traditional 8086 series CPU system bus with ISA bus, EISA bus, and so on. ISA bus is 16-bit system bus, the operating frequency is 8MHz, the data transfer rate of 16MB / s. EISA is an extension based on the ISA data bus width of 32-bit open bus standards. Maximum transmission rate of up to 33MB / s. However, due to I / O speed is relatively low, the two bus technology has gradually been phased out.

AMBA has many third-party support for ARM-based processor core in SoC design, has become a widely supported one of the existing Internet standards. AMBA 2.0 bus standard defines three groups: AHB (AMBA high performance bus), ASB (AMBA system bus), and APB (AMBA Peripheral Bus). AHB bus architecture used to interconnect with the master module and the traditional shared bus model from the module, interface and interconnect separation, which is the interconnection between the chip module is important. Therefore, this paper comply with the selected bus AHB bus transfer the basic norms, and on this basis, the characteristics for 8086CPU additions and amendments to some of the bus interface. The design includes two aspects: AHB and 8086 transmission timing of the match; based 8086CPU expansion bus interface design. Bus structure shown in Figure 3.


3.2.2 transmission timing of the matches

because the AHB bus and CPUs transfer protocol are different, so the timing needs to match the two interfaces to ensure the CPU and other peripheral IP can communicate via the bus properly. Related Interface Control signals shown in Table 1.


interface module to determine the first visit under the MIO signal is memory or I / O devices, and if I / O devices, when the sample to the READY signal is high, to get control of the AHB bus, and peripheral I / O devices to communicate. Designed state machine shown in Figure 4.


T1: According to MIO signal to determine whether the current CPU access to peripheral I / O. If 8086 is the processor core to access memory cells rather than the device on the AHB bus (the MIO 1), the state machine will remain T1 state, and does not send the bus to the AHB bus request signal (ie HBUSREQ signal set to 0). MIO is low then jump to the T2.

T2: the state machine into the T2 state, send the bus to the AHB bus request signal (ie HBUSREQ signal is set to 1), AHB bus arbiter to request access to the bus. READY signal is detected at the same time, when the READY signal is detected high, the AHB bus arbiter to the bus access to the 8086 processor core, the state machine to enter the next rising edge of clock T3 state. Conversely, if the READY has been low, saying that the 8086 CPU to access the AHB bus slave device is not ready to require 8086 processor cores into a wait state, the state machine remains unchanged T2 state.

T3: CPU through the AHB bus and peripheral IP to communicate, until the end of the communication, to return to the T1 state.

8086 processor core to read and write signals by the READY signal control, when the READY signal is high, it can transmit and receive data, or read and write signals remain. READY signal from the AHB bus transfer from the device to complete the signal HREADYIn, AHB bus, and from the device to allow signals HGRANT HRESP together determine the signal response. The read and write control signals on the bus by the combinational logic generated HWRITE. The pseudo-code generation process shown in Table 2.


3.2.3 Bus Interface extension

8086CPU addition to the data and address bus and literacy and other major control signal READY, there is an interrupt, and external DMA request and response-related equipment, port signal. These signals are not available in the standard AHB bus, and therefore needs to be expanded bus interface to match the 8086 CPU. Expansion bus interface design includes two parts: the interrupt handling and DMA data channel. 8086 CPU interrupt and DMA on the port signals as shown in Table 4.


system bus peripheral interrupt request is received after the interrupt request made to the CPU, once interrupt response is received, sent to the peripheral interrupt signal, modify the decoding unit, the peripheral gating to ensure that during the second interrupt can interrupt type number sent via the bus CPU, so CPU can successfully jump Go to the interrupt service routine.

DMA controller performs data transfer, you need to master the control of the AHB bus to the on-chip memory or other peripherals on the bus address and control signals issued, which is equivalent to the main AMBA equipment; the other hand, in the DMA controller before starting work, CPU needs to be pre-operation to make it in accordance with the specific configuration parameters work in the initialization phase, CPU is the master on the AHB bus, DMA controller is from equipment. This DMA controller on two sides, the design of the bus is equipped with a special DMA channel and its matched: CPU normal operation,

DMA from the device to play the role of the initial acceptance of its CPU ; by HLDA to arbitration signal response when the CPU peripheral DMA request (ie, HLDA is high), to give control to the peripheral bus, using DMA data channel to transmit data, transmit the same to comply with the agreement AMBA protocol. State of the bus timing control module shown in Figure 5.



3.3 Interface Design of the storage unit

memory subsystem consists of a RAM and a ROM, 8086CPU supports 20-bit address bus, with 1M byte of memory space is divided into RAM and ROM area district. In this paper, the development boards allocation of resources into on-chip ROM format 16k * 16 ROM as a memory cell, using DE2 development board configured as 8M of SDRAM 256K * 16 bit bus format instead of the RAM memory unit.

pieces in a variety of random access memory, SDRAM low price, small size, high speed, large capacity, is an ideal device. However, more complex control logic SDRAM, very strict requirements on the timing, which requires a dedicated controller: control SDRAM initialization, refresh, and pre-washed and basic reading and writing. Meanwhile, the need to match the SDRAM controller and the 8086 CPU read and write timing. Concrete implementation of this interface state machine shown in Figure 6.


T1: When RDY is high, first determine the read or write operation, then DONE 0: Read: Set WR = 0, RD = 1; write: set WR = 1, RD = 0.

T2: when the DONE signal is high, that can be read / write operations, to jump to T3.

T3: CPU SDRAM via SDRAM controller read and write.

T4: When the low byte valid signal bwl_n is high, the implementation of the low-byte transfer.

T5: When the high byte effective signal bwh_n is high, the implementation of high-byte transfer.

T6: CPU to complete read and write operations, the relevant control signal cleared.

which, DONE signal to indicate whether the reading and writing done, DONE is high that only read and write to complete before the next write operation. RDY signal indicates CPU SDRAM is ready to accept the access, the write request signal from the SDRAM (IN_REQ = 1) and read the effective signal (OUT_VALID = 1) joint control, and its pseudo-code generation process as shown in Table 5.


single-chip computer based on system-level design of the structure, calls have been prepared for 8086 IP soft core , 8255 IP soft core, SDRAM controller, SDRAM model IS42S16400, AHB Bus IP soft core and decoder IP soft core.

connected to the related input and output ports, while the input port 8086 related to the assignment, the unused output port vacant, single-chip computer system to complete RTL-level design.

4 single-chip computer system simulation and verification

single-chip computer designed RTL-level design is all part of the process, to ensure the success of the final design, they must be comprehensive software simulation and hardware verification, including test platform to build, design and analysis of simulation results of the test plan, implement FPGA verification.

4.1 test program design

application circuit containing the 8255 single-chip computer system based on completed structures, required to achieve the eight off control of eight LED lights off function. 8255 switch connected to eight of the PA0 ~ PA7; will connect eight LED lamp drive circuit 8255 of the PC0 ~ PC7. Under the control of the 8086 CPU, read through the bus connection port in the 8255 PA eight switch, the switch to the value sent to the SDRAM memory, and then read from the SDRAM sent to the 8255 PC switch port, to drive eight LED lights bright or off.

4.2 Simulation Results Analysis

the smallest single-chip computer, set the RTL level simulation waveforms shown in Figure 7. Under the control of the 8086 CPU, 8255 interface read port connected to the 8255 PA after eight switch 11000010, send it to 8255s PC port, the driver output logic value of 11,000,010.



successfully compiled using the Quartus II software will be designed to generate route downloaded to the FPGA, the results obtained with the design equivalent the actual circuit, the circuit with the actual test system for testing, which verifies the correctness of the design. Verification of the FPGA logic analyzer to read Results display shown in Figure 8.



5 Conclusion

the paper-based IC design methodology, under the guidance of the 8086 CPU core based single-chip architecture computer platform to study with the AMBA bus, SDRAM, 8255 and other external IP integration. On this basis, the design is based on 8086 IP soft-core single-chip computer systems, and implementation of FPGA capabilities demonstration. In subsequent work, will consider further expansion peripheral interface IP soft-core CPU; integrated DMA controller, to achieve VGA display; the DOS operating system to join the 8086 single-chip computer platforms and operating system device drivers and applications software.

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