Category:
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
0
1
2
3
4
5
6
7
8
9
Position:IcFull.com » IC Electronic information » Category: 0

IC Electronic information

0.18μm copper dual damascene process in space imaging (a)

In Electronic Infomation Category: 0 | on November 14,2010

1. AMD Saxony Manufacturing Co., Dresden D-01109, Germany; 2. AMD technology R & D Group, Sunnyvale, California; 3. KLA-Tencor, Migdal HaEmek 23100, Israel)


Overview: Because of the space imaging overlay (Ovcrlay) technology budget With the integrated circuit (IC) design specifications of austerity and IR2153S datasheet and tight, therefore, Overlay accuracy measuring the importance of technology increases. After the development by (After Develop DI) stage and IR2153S price and after etching (After Etch FI) phase of the Overlay measurement results were compared to study design under 0.18μm copper dual damascene process in Owrlay accuracy. On the same wafer to ensure post-development (DI) stage and IR2153S suppliers and post-etch (FI) phase of the test conditions, we finished the 5 layers, the wafer were compared. In addition, use of CD-SEM (width of a scanning electron microscope) measured a process layer (Poly Gate) chip on the Overlay, and with the split line method using the optical measurement results were compared Overlay. Found that the calibration of the chip overlay there are serious limitations in the application of CD-SEM that the lack of a suitable structure Overlay measurement. We will also continue as we provide quantitative comparisons, but also to recommend combinations of CD-SEM measurement of the structure so that it can be applied to the design of future lithography.

Key words: spatial imaging overlay; accuracy; calibration

Key words: TN305.7 Document code: A Article ID :1004 -4507 (2005) 02 - 0015-07

now commonly used in lithography is the development phase after the split line using a special measure within the Overlay graph structure meter measurements. In the application of this method, provided that the assumed measured by dividing line graph structure within the Overlay measurements can truly reflect the status of the device Overlay. However, due to increasingly tight design specifications, the dividing line, the large box-in-box or a bar-in-bar structure and a smaller difference between the device structure is increasingly obvious. This difference may lead to foot problems: in the actual production process, using dividing lines on the box-in-box structure of the Overlay measurements are able to continue to truly reflect the status of the device Overlay towel. Studies conducted earlier showed that [1,5], the Overlay measurement in the production process may lead to unnecessary errors, and these errors in the measurement process is difficult Overlay captured the.

AMD company is located in the city of Dresden, Germany, Fab 30, a few days ago with 0.18μm process using copper dual damascene technology to produce logic integrated circuits. Overlay of control despite the current level of technology is already quite good, but still question the need for systematic Overlay and the "invisible error" [1] make reasonable judgments, especially when the design constraints to the 0.13μm level, this A demand will become particularly prominent. Moreover, the advanced process control on the Overlay applications, such as the Overlay accurate measurement, will be the top priority needs. The effect of these applications will be strictly dependent on the quality of the data used Overlay.

usually need to calibrate the accuracy of manual data or independent reference measurement method. So far, the calibration of the Overlay standards or not available. Moreover, even if available, technical standards and equipment can only be read to determine the degree of consistency between the values. Moreover, whether measured by dividing line within the Overlay graph structure measurements can accurately reflect the status of the device Overlay divination, the problem remains unresolved. Other devices can be in the real structure of the information collected on the independent measurement Overlay also need to address this issue. Compared with the optical measurement method, almost all of the available reference methods (eg AFM) there was a fatal flaw, that is, output is very low. In the research process, we are still within a reasonable time span, the use of automated CD-SEM (width - scanning electron microscope) to generate a benchmark Overlay measurement method.

of Overlay accuracy (or reduce the accuracy) of the main factors shown in Figure 1. Such as the TIS (caused by the testing means testing offset), TIS-3σ (TIS variation on the wafer), tools, and tools and measure the matching degree of accuracy (which can be repeated), and other factors are derived from the Overlay Measurement Tool . The other two factors are characteristics of the wafer, stepper and process decisions:

(1) DI / FI offset (DI / FIBias), the "DI-FI" said that the DI-Overlay and FI- Overlay of the difference:
(2) Over] ay is the difference between the line with a split die Overlay measurement and measurement of the difference between the structure of the device to "In-die" said.

known, DI / FIBias is present in the aluminum process technology issues 12-41 late. Because copper dual damascene metal deposition techniques and process definition of a completely different role, so DI / FI Bias is expected to improve. However, in order to determine the DI / FI Bias Overlay accuracy of the impact of the budget, we must study its characteristics. Overlay with a split line measurement and die (or chip overlay) is the difference between a matter of concern [5], and with the design size constraints of the problem will become increasingly prominent.

In this paper, elaborated on the 0.18μm design standards used in dual damascene copper process technology, layer 5 made of DI / FI Bias measurements. Unable to find the appropriate measure, were only one level of the dividing line and measure the difference between die. Overlay tool will measure the performance results with the combination of on the 0.18μm design standards can be used in copper dual damascene technology, a comprehensive description of the composition of Overlay accuracy. 7 also determine the design of future lithography due to the combination of CD-SEM measurement of the structure of demand.

1 Optical Overlay measurement

Optical Overlay The purpose of measurement tools is clear Bn independent factors to the accuracy, and to quantify the difference between DI-FI. Optical FI-Overlay of the data also be used as a measure of dividing lines lie on the bare chip C higher than the data. Most optical measurements in the AMD/Fab30 Overlay KLA5200XP device on the wafer fab. In order to obtain cross-version of the tool and the tool between the comparison, we also used the KIA-Tencors new Archer10 equipment manufacturer ancillary measurements.

take into account the complexity of the manufacturing process, we only selected 5 representative of the wafer layer, respectively-PolyGate, LoCal Interconnect, Contact, Via 2 and Metal 3. This five layer etching operation will be implemented. They represent different stages of the manufacturing cycle (the production line early, mid and late), and can show the difference between object design Overlay.

Overlay program is generated through the standard procedure. After defined in the protocol development phase for (DI) and post-etching phase (FI) of the nine test areas within the unified graphics and 5 regional test objects. All programs are in line with the proven accuracy, TIS, and TIS-3s requirements. As the special needs of this project, we also made some non-standard for each level of measurement, namely:

(1) collected during exposure of the Overlay the data to determine the value set under the Overlay focus on the effect of measurement tool;
(2) were tested for each measurement point TIS value to assess the average TIS TIS point by point calibration and calibration results.

1.1 build FI benchmark

Overlay for the optical measurement of overlay accuracy measurement is an important factor is the DI and FI measured difference. In the DI stage, usually before the one (queue base) layer box (or bars) will be covered with a layer of film (laminated), and then forming the etching in the next stage. In the film, interference or other steps may exist in the asymmetric factors will lead to failure of or interference Overlay measurements. Overlay and because of FI phase is clear, there are clearly defined and easy comparison, so consider as a reliable benchmark FI Overlay layer.

order to verify the validity of this benchmark, provided full use of the KLA5200XP method to measure various metrics FI Overlay, while recording the measurement results of the focal length of the Overlay. Figure 2 shows the use of Single Focus (single focal length) method, which KLA5200XP the "SingleGrab" Poly Gate layer obtained by the standard Overlay data. In order to expand the scale, and in order to make the changes Overlay function of focus is more sensitive to the standard Overlay each point is defined as zero at zero focus conditions.

Figure 9 of the wafer lines correspond to the nine measurement points on the test results is the change in focal length range is ± 500nm obtained under the conditions. Through the icons, can be observed for each measurement point, Overlay data with the measured changes in focal length produced only 1-2nm of change, that Overlay is not dependent on the focal length varies. Figure 3 shows the two measurement methods used to obtain the Poly Gate FI Overlay the difference between the data, these two methods are: Single Focus and Double Focus, Double Focus that KLA5200XP the "Double Grab". Can be seen that the difference between the two approaches zero when the focal length range of ± 2nm, when the focus beyond the zero range, the difference may be slightly higher. Single Focus and Double Focus as there is no apparent conflict, so that the focus will be zero when the Single Focus FI Overlay obtained FI baseline data as more desirable. Testing and other layers are also obtained similar results.

1.2 DI / FI Bias

available through the following methods DI / FI Bias:

(1) at the DI stage, the wafers will be marked on the serial number and batch number ;
(2) using standard measurement Overlay data sampling program;
(3) to continue this batch wafer etching operation;
(4) Upon completion of the etching process, the sampling phase is extracted DI the same wafer;
(5) on the wafer stage and the same position measurement DI FI Overlay data.

of five layers, obtained by measuring the worst DI / FI Bias results shown in Table 1. The table lists the average TIS calibrated using average-TIS calibration (the calibration wafer TIS average of all points), and TIS-by-point calibration site-by-site TIS calibration results. TIS can see point by point through the calibration method can reduce the deviation of 2-3nm.

1.3 DI / FI Bias and its impact on the modeling Overlay

analysis by stepper can also learn DI / FIBias other effects: We were the two layer (Poly Gate and Local Interconnect ) calculated the DI and the case of stepper n amendment. To simplify the comparison process, only the report of the instrument under the applicable Overlay model to predict the exposure should be out Interfield (Internet zone) and Intrafield (internal region) in the maximum difference between DI and FI Overlay, the boundary of the wafer (Interfield) and regional boundary (Intrafield) calculate the maximum value. To facilitate the analysis, using the KLA-Tencor produced KLASS4. Calculation process for the next:

(1) analysis of DI Overlay data, generate stepper correction;
(2) calculate the maximum expected error of Overlay, in the inter-field and intrafield case only modeling the error as the basis;
(3) of the n data, repeat steps 1-2:
(4) calculation of steps 2 and 3, the difference between the results.
DI / FI maximum difference shown in Table 2.

1.4 wafer DI / FIBias

part of the wafer, said test results came out with the help of vector. PolyGate and Contact layers DI / FI Bias comparison shown in Figure 4. Although both cases, DI / FI Bias maximum is about 10nm, but the state is somewhat different: in the Poly Gate layer, wafer DI / FI Bias is random, and in the Contact layer It is the spiral, and that a process (possibly CMP) on the DI / FI Bias had an impact.

1.5 tools and tool matching degree

match the tools and instruments is one of the factors of accuracy, so we use the new KLA-Tencor manufacturer of process measurement equipment Archer10 subset of layers . The worst outcome (ie, minimum and maximum) in Figure 5. For most layer, the two version of a tool is about the worst match as 5nm. Only the Poly-DI layer worst result is 10nm. As shown in Figure 6, the difference between the vector tools and instruments can be seen, the local maximum within the region (0, -2) reflects to some extent exacerbated by the difference between tools and instruments. More research shows that lead is due to a difference in increasing process caused important changes in Overlay object.

(unfinished)

IR2153S datasheetIR2153S suppliersIR2153S Price

Related technical information

All right reserved:icfull.com © 2010-2016 Certificate